公开(公告)号：US20170271474A1

公开(公告)日：2017-09-21

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1−xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1−xA, wherein x is not 0.53.

公开(公告)号：US20170148922A1

公开(公告)日：2017-05-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78645

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US09490323B2

公开(公告)日：2016-11-08

申请号：US14722402

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Rwik Sengupta

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/16 ,  H01L21/8238

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775

Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

Abstract translation: 包括堆叠的纳米片场效应晶体管（FET）的器件可以包括衬底，衬底上的第一沟道图案，第一沟道图案上的第二沟道图案，被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

公开(公告)号：US20240256848A1

公开(公告)日：2024-08-01

申请号：US18632180

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US11727258B2

公开(公告)日：2023-08-15

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: G06N3/063 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78391

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20230206053A1

公开(公告)日：2023-06-29

申请号：US18111471

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L29/808 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/8083 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/42324 ,  H01L29/40114 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US20230004789A1

公开(公告)日：2023-01-05

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US11476121B2

公开(公告)日：2022-10-18

申请号：US16551028

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US11290110B2

公开(公告)日：2022-03-29

申请号：US15886179

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H03K19/21 ,  G06N3/063 ,  H03K19/18

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

公开(公告)号：US20210117769A1

公开(公告)日：2021-04-22

申请号：US17133427

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  G06N3/04 ,  H01L27/112 ,  H01L27/11556 ,  G06N3/08

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.