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    Magnetic element with storage layer materials
    61.
    发明授权
    Magnetic element with storage layer materials 有权
    磁性元件与存储层材料

    公开(公告)号：US08823120B2

    公开(公告)日：2014-09-02

    申请号：US13959710

    申请日：2013-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

    IPC: H01L29/82 ,  G11C11/15

    CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/12

    Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

    Abstract translation: 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

    SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL
    62.
    发明申请
    SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL 有权
    编程存储器单元的系统和方法

    公开(公告)号：US20140219015A1

    公开(公告)日：2014-08-07

    申请号：US13759310

    申请日：2013-02-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    IPC: G11C7/00 ,  G11C11/40

    CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

    Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

    Abstract translation: 一种方法包括在包括重叠区域和沟道区域的半导体晶体管结构下产生击穿条件。 通过使半导体晶体管结构的栅极和重叠区域之间的第一电压差超过半导体晶体管结构的击穿电压，同时保持栅极和沟道区域之间的第二电压差小于 击穿电压。

    MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION
    63.
    发明申请
    MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION 有权
    MRAM设备和集成技术兼容逻辑整合

    公开(公告)号：US20140147941A1

    公开(公告)日：2014-05-29

    申请号：US14172208

    申请日：2014-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

    Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

    Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

    FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE
    64.
    发明申请
    FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE 有权
    一种磁性隧道连接装置的制造

    公开(公告)号：US20140038312A1

    公开(公告)日：2014-02-06

    申请号：US14048918

    申请日：2013-10-08

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

    IPC: H01L43/02

    CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

    Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使所述处理器启动所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

    HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE
    65.
    发明申请
    HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE 有权
    分层存储器磁阻随机存取存储器（MRAM）架构

    公开(公告)号：US20130279244A1

    公开(公告)日：2013-10-24

    申请号：US13842122

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seung H. Kang ,  Xiaochun Zhu

    IPC: G11C11/16 ,  H01L43/02

    CPC classification number: G11C11/161 ,  G06F12/0811 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/222 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/02

    Abstract: A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency.

    Abstract translation: 公开了分层存储器磁阻随机存取存储器架构。 在特定实施例中，装置包括对应于分层存储器系统中的第一级的第一磁阻随机存取存储器（MRAM）装置。 该装置包括对应于分级存储器系统中的第二级的第二MRAM设备。 第一MRAM设备具有第一访问延迟并且包括具有第一物理配置的第一磁隧道结（MTJ）设备。 第二MRAM设备具有第二接入延迟并且包括具有第二物理配置的第二WI设备。 第一个访问延迟小于第二个访问延迟。

    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION
    66.
    发明申请
    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 有权
    磁性隧道连接装置和制造

    公开(公告)号：US20130235656A1

    公开(公告)日：2013-09-12

    申请号：US13872338

    申请日：2013-04-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    IPC: H01L43/02 ,  G11C11/15

    CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

    Abstract translation: 一种装置包括包括围绕金属垫的底盖层的结构。 该装置还包括磁隧道结（MTJ）装置，其包括耦合到该结构的底部电极。 MTJ装置包括磁性隧道结层，顶部电极和逻辑帽层。 MTJ装置相对于金属垫偏移。

    Perpendicular magnetic tunnel junction (pMTJ) devices employing a thin pinned layer stack and providing a transitioning start to a body-centered cubic (BCC) crystalline / amorphous structure below an upper anti-parallel (AP) layer
    69.
    发明授权
    Perpendicular magnetic tunnel junction (pMTJ) devices employing a thin pinned layer stack and providing a transitioning start to a body-centered cubic (BCC) crystalline / amorphous structure below an upper anti-parallel (AP) layer 有权
    垂直磁性隧道结（pMTJ）器件采用薄的钉扎层堆叠，并提供了一个向上反向平行（AP）层下方的体心立方（BCC）结晶/非晶结构的转变开始

    公开(公告)号：US09590010B1

    公开(公告)日：2017-03-07

    申请号：US15079634

    申请日：2016-03-24

    Applicant: QUALCOMM Incorporated

    Inventor： Matthias Georg Gottwald ,  Jimmy Jianan Kan ,  Chando Park ,  Xiaochun Zhu ,  Seung Hyuk Kang

    IPC: H01L29/66 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16

    CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L27/11582 ,  H01L28/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: Perpendicular magnetic tunnel junction (pMTJ) devices employing a pinned layer stack with a thin top anti-parallel (AP2) layer and having a transitioning layer providing a transitioning start to a body-centered cubic (BCC) crystalline/amorphous structure below the top anti-parallel (AP2) layer, to promote a high tunnel magnetoresistance ratio (TMR) with reduced pinned layer thickness are disclosed. A first anti-parallel (AP) ferromagnetic (AP1) layer in a pinned layer has a face-centered cubic (FCC) or hexagonal closed packed (HCP) crystalline structure. A transitioning material (e.g., Iron (Fe)) is provided in a transitioning layer between the AP1 layer and an AFC layer (e.g., Chromium (Cr)) that starts a transition from a FCC or HCP crystalline structure, to a BCC crystalline/amorphous structure. In this manner, a second AP ferromagnetic (AP2) layer disposed on the AFC layer can be provided in a reduced thickness BCC crystalline or amorphous structure to provide a high TMR with a reduced pinned layer thickness.

    Abstract translation: 垂直磁性隧道结（pMTJ）器件采用具有薄顶部反平行（AP2）层的钉扎层叠层，并且具有向顶部抗反射平面（AP2）层下方的体心立方（BCC）结晶/非晶结构提供过渡开始的过渡层 公开了平行（AP2）层，以促进具有减小的钉扎层厚度的高隧道磁阻比（TMR）。 固定层中的第一反平行（AP）铁磁（AP1）层具有面心立方（FCC）或六边形封闭（HCP）晶体结构。 在AP1层和开始从FCC或HCP晶体结构的转变到BCC晶体/晶体的AFC层（例如，铬（Cr））之间的过渡层中提供了转变材料（例如，铁（Fe） 无定形结构。 以这种方式，设置在AFC层上的第二AP铁磁（AP2）层可以以减小的厚度BCC晶体或非晶结构提供，以提供具有减小的钉扎层厚度的高TMR。

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