公开(公告)号：US08698252B2

公开(公告)日：2014-04-15

申请号：US13456939

申请日：2012-04-26

申请人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/11

CPC分类号： H01L21/823842 ,  H01L21/28158 ,  H01L21/823857 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US20140042524A1

公开(公告)日：2014-02-13

申请号：US13568997

申请日：2012-08-07

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28114 ,  H01L21/76885 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376

摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.

摘要翻译： 一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。 锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

公开(公告)号：US20120319238A1

公开(公告)日：2012-12-20

申请号：US13160096

申请日：2011-06-14

申请人： Hak-Lay Chuang ,  Ming Zhu

发明人： Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L29/02 ,  H01L21/28

CPC分类号： H01L28/60 ,  H01L21/823437 ,  H01L29/66181 ,  H01L29/94

摘要： An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.

摘要翻译： 公开了一种集成电路器件及其制造方法。 在一个示例中，集成电路器件包括具有设置在半导体衬底中的掺杂区域的电容器，设置在掺杂区域上的电介质层和设置在电介质层上的电极。 至少有一个帖子功能嵌入电极。

公开(公告)号：US20070239946A1

公开(公告)日：2007-10-11

申请号：US11403146

申请日：2006-04-11

申请人： Ming Zhu

发明人： Ming Zhu

IPC分类号： G06F13/00

CPC分类号： G06F11/1451

摘要： Storage using resemblance of data segments is disclosed. It is determined that a new segment resembles a second prior stored segment wherein the second prior stored segment is represented as a first stored delta and a first prior stored segment. A second delta between the new segment and the prior stored segment is determined. A representation of the new segment based at least in part on the second delta is stored.

摘要翻译： 公开了与数据段相似的存储。 确定新的段类似于第二先前存储的段，其中第二先前存储的段被表示为第一存储的增量和第一先前存储的段。 确定新段和先前存储段之间的第二增量。 存储至少部分地基于第二增量的新段的表示。

公开(公告)号：US20050043224A1

公开(公告)日：2005-02-24

申请号：US10881028

申请日：2004-06-30

申请人： William Fahl ,  Nalini Raghavachari ,  Ming Zhu ,  John Kink

发明人： William Fahl ,  Nalini Raghavachari ,  Ming Zhu ,  John Kink

IPC分类号： G01N33/483 ,  A61K9/08 ,  A61K9/107 ,  A61K9/127 ,  A61K9/66 ,  A61K31/015 ,  A61K31/05 ,  A61K31/085 ,  A61K31/21 ,  A61K31/352 ,  A61K31/428 ,  A61K31/497 ,  A61K45/00 ,  A61K47/10 ,  A61K47/14 ,  A61K47/24 ,  A61K47/34 ,  A61P35/00 ,  A61P39/00 ,  G01N21/77 ,  G01N21/78 ,  G01N33/15 ,  G01N33/50 ,  A61K38/17 ,  A61K31/7076 ,  A61K31/704 ,  A61K31/7048 ,  A61K31/7072 ,  A61K31/4745

CPC分类号： A61K31/497 ,  A61K9/127 ,  A61K9/1272 ,  A61K35/36

摘要： Compositions, pharmaceutical preparations and methods are disclosed for protecting non-neoplastic cells from damage caused by cancer chemotherapeutic agents or radiation therapy, during the course of cancer therapy or bone marrow transplant. These are based on the use of chemoprotective inducing agents that induce or increase production of cellular detoxification enzymes in target cell populations. The compositions and methods are useful to reduce or prevent hair loss, gastrointestinal distress and lesions of the skin and oral mucosa that commonly occur in patients undergoing cancer therapy. Also disclosed is a novel assay system for identifying new chemoprotective inducing agents.

摘要翻译： 公开了用于在癌症治疗或骨髓移植过程中保护非肿瘤细胞免受由癌症化学治疗剂或放射治疗引起的损伤的组合物，药物制剂和方法。 这些是基于在靶细胞群体中诱导或增加细胞解毒酶的产生的化学保护诱导剂的用途。 组合物和方法可用于减少或预防通常在经历癌症治疗的患者中发生的脱发，胃肠道窘迫和皮肤和口腔粘膜的损伤。 还公开了用于鉴定新的化学保护诱导剂的新型测定系统。

公开(公告)号：US09292364B1

公开(公告)日：2016-03-22

申请号：US14494457

申请日：2014-09-23

申请人： Mario Linge ,  Ananda Kumar Gajula ,  Jianxun Zhou ,  Oscar Marquez ,  Xiaojun Feng ,  Yang-cheng Fan ,  Ming Zhu ,  Paul Xi ,  Marco Eidinger ,  Mohamed Elzankaly

发明人： Mario Linge ,  Ananda Kumar Gajula ,  Jianxun Zhou ,  Oscar Marquez ,  Xiaojun Feng ,  Yang-cheng Fan ,  Ming Zhu ,  Paul Xi ,  Marco Eidinger ,  Mohamed Elzankaly

IPC分类号： G06F13/00 ,  G06F9/54

CPC分类号： G06F9/542

摘要： A technique is described providing offline support to business applications. Offline support allows a business application running on a portable electronic device without connectivity to a backend server to operate as though the business application has access to a backend server. The technique receives a client request to operate the application in an offline mode. The technique then retrieves a business object to be utilized in the offline mode and an event trigger for interacting with the business object. The native programming language is then determined and then an event handler written in a native language of the client device and that is associated with the event trigger is retrieved. The event trigger is then modified to point to the event handler. The business object, event trigger, and event handler are then packaged together.

摘要翻译： 描述了一种提供对业务应用程序的离线支持的技术。 离线支持允许在便携式电子设备上运行的业务应用程序，而无需连接到后端服务器，就像业务应用程序可以访问后端服务器一样进行操作。 该技术接收客户端请求以在离线模式下操作应用程序。 然后，该技术检索要在离线模式中使用的业务对象和用于与业务对象交互的事件触发器。 然后确定本地编程语言，然后检索用客户端设备的本机语言编写并与事件触发相关联的事件处理程序。 然后将事件触发器修改为指向事件处理程序。 然后将业务对象，事件触发器和事件处理程序打包在一起。

公开(公告)号：US09257347B2

公开(公告)日：2016-02-09

申请号：US13599642

申请日：2012-08-30

申请人： Hak-Lay Chuang ,  Ming Zhu

发明人： Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L27/112 ,  H01L29/423

CPC分类号： H01L21/823814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/11273 ,  H01L29/42392

摘要： A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having a raised drain structure is also disclosed.

摘要翻译： 公开了一种形成具有升高的漏极结构的场效应晶体管的方法。 该方法包括：通过蚀刻半导体衬底来形成截头圆锥形源，所述截头圆锥形源突出在所述半导体衬底的平坦表面上方; 形成晶体管栅极，所述晶体管栅极的第一部分围绕所述截头圆锥形源的一部分，并且所述栅极的第二部分被配置为耦合到第一电触头; 以及形成具有凸起部分的漏极，所述凸起部分被配置为耦合到第二电接触并且位于与所述晶体管栅极的第二部分在所述半导体衬底的平面表面上方相同的高度处。 还公开了一种具有升高的漏极结构的半导体器件。

公开(公告)号：US08742492B2

公开(公告)日：2014-06-03

申请号：US13568997

申请日：2012-08-07

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/28114 ,  H01L21/76885 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376

摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.

摘要翻译： 一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。 锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

公开(公告)号：US20130270647A1

公开(公告)日：2013-10-17

申请号：US13448846

申请日：2012-04-17

申请人： Ming Zhu ,  Jin-Aun Ng ,  Chi-Wen Liu

发明人： Ming Zhu ,  Jin-Aun Ng ,  Chi-Wen Liu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/022 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.

公开(公告)号：US20130154021A1

公开(公告)日：2013-06-20

申请号：US13328382

申请日：2011-12-16

申请人： Hak-Lay Chuang ,  Ming Zhu

发明人： Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857

摘要： The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 在衬底上形成高k电介质层。 在高k电介质层的一部分上形成第一覆盖层。 在第一覆盖层和高k电介质层上形成第二覆盖层。 在第二盖层上形成虚拟栅电极层。 对虚拟栅极电极层，第二覆盖层，第一覆盖层和高k电介质层进行构图以形成NMOS栅极和PMOS栅极。 NMOS栅极包括第一覆盖层，PMOS栅极不含第一覆盖层。 去除PMOS栅极的伪栅极电极层，从而暴露PMOS栅极的第二覆盖层。 PMOS栅极的第二覆盖层被转换成第三覆盖层。