公开(公告)号：US07781848B2

公开(公告)日：2010-08-24

申请号：US11704924

申请日：2007-02-12

Applicant: Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

Inventor： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC: H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

Abstract translation: 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20100193874A1

公开(公告)日：2010-08-05

申请号：US12757658

申请日：2010-04-09

Applicant: Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

Inventor： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC: H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

Abstract translation: 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US07652328B2

公开(公告)日：2010-01-26

申请号：US11705792

申请日：2007-02-14

Applicant: Hiroyuki Yamasaki ,  Kouji Matsuo ,  Seiichi Iwasa

Inventor： Hiroyuki Yamasaki ,  Kouji Matsuo ,  Seiichi Iwasa

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7843 ,  H01L21/2254 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes an isolation region, a semiconductor element region defined by the isolation region, and having a channel forming portion and a recessed portion, the recessed portion being formed between the isolation region and the channel forming portion, and an epitaxial semiconductor portion formed in the recessed portion, wherein the semiconductor element region has a wall portion between the isolation region and the epitaxial semiconductor portion.

Abstract translation: 半导体器件包括隔离区，由隔离区限定的半导体元件区，并具有沟道形成部和凹部，凹部形成在隔离区与沟道形成部之间，形成外延半导体部 在所述凹部中，所述半导体元件区域在所述隔离区域和所述外延半导体部分之间具有壁部。

公开(公告)号：US07579231B2

公开(公告)日：2009-08-25

申请号：US10815932

申请日：2004-04-02

Applicant: Kouji Matsuo ,  Tomohiro Saito ,  Kyoichi Suguro ,  Shinichi Nakamura

Inventor： Kouji Matsuo ,  Tomohiro Saito ,  Kyoichi Suguro ,  Shinichi Nakamura

IPC: H01L21/8238 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/62

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/31683 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.

Abstract translation: 公开了一种制造半导体器件的方法，包括在半导体衬底上直接或间接形成金属化合物膜，通过氧化金属化合物膜形成由金属氧化物膜或金属硅酸盐膜构成的含金属的绝缘膜，以及 在含金属的绝缘膜上形成电极。

公开(公告)号：US20090139449A1

公开(公告)日：2009-06-04

申请号：US12289895

申请日：2008-11-06

Applicant: Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

Inventor： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

IPC: B05C11/00

CPC classification number: B82Y10/00 ,  C23C14/042 ,  C23C14/48 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01L21/266 ,  Y10T428/24273

Abstract: Preparing a stencil mask comprising a silicon thin film in which an opening for selectively irradiating charged particles to a semiconductor substrate is provided and whose irradiation surface on which the charged particles are irradiated is implanted with an impurity, and selectively irradiating charged particles to the semiconductor substrate using the stencil mask which is opposingly arranged on the semiconductor substrate.

Abstract translation: 制备包括硅薄膜的模板掩模，其中用于选择性地将带电粒子照射到半导体基板的开口，并且其上照射有带电粒子的照射面被注入杂质，并且将带电粒子选择性地照射到半导体衬底 使用相对设置在半导体衬底上的模板掩模。

公开(公告)号：US07341650B2

公开(公告)日：2008-03-11

申请号：US10875272

申请日：2004-06-25

Applicant: Kouji Matsuo ,  Satoshi Ishikawa

Inventor： Kouji Matsuo ,  Satoshi Ishikawa

IPC: G01N27/60

CPC classification number: G01N27/4077 ,  Y10T29/49929

Abstract: In a method of manufacturing a sensor, firstly, a plate-type detection element is inserted through an element-insertion through-hole of a first powder-compacted ring. Secondly, a flange section including at least the first powder-compacted ring is integrally assembled to the plate-type detection element, applying axially compressive pressure to the first powder-compacted ring so as to compressively deform the first powder-compacted ring such that the cross-sectional area of the element-insertion through-hole is reduced. Thirdly, the flange section is engaged, directly or via an intermediate member, with the stepped portion of the metallic shell at the time of disposing of the plate-type detection element in the through-hole of the metallic shell. A sensor prepared by the method is also disclosed.

Abstract translation: 在制造传感器的方法中，首先，通过第一粉末压实环的元件插入通孔插入板型检测元件。 其次，至少包括第一粉末压实环的凸缘部分一体地组装到板式检测元件上，对第一粉末压实环施加轴向压缩压力，以使第一粉末压实环压缩变形，使得 元件插入通孔的横截面积减小。 第三，当将板状检测元件设置在金属外壳的通孔中时，凸缘部分直接或经由中间构件与金属外壳的台阶部分接合。 还公开了通过该方法制备的传感器。

公开(公告)号：US20070172997A1

公开(公告)日：2007-07-26

申请号：US11715965

申请日：2007-03-09

Applicant: Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

Inventor： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

IPC: H01L21/8232

CPC classification number: H01L29/66575 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1033 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/926

Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.

Abstract translation: 提供了一种半导体器件，包括衬底，在衬底上形成的器件隔离绝缘膜，形成在衬底上的栅电极，形成在器件隔离绝缘膜中并连接到栅电极的栅极布线层，源极和漏极 布置在基板上，经由栅极电极相对对置;以及绝缘膜，其覆盖栅极电极和栅极布线层中的每一个的底部和侧面，其中栅极，源极和漏极以及栅极布线层具有上表面水平 等于或低于器件绝缘膜的绝缘膜。

公开(公告)号：US20070111114A1

公开(公告)日：2007-05-17

申请号：US11648564

申请日：2007-01-03

Applicant: Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

Inventor： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

IPC: G03F1/00 ,  G03C5/00

CPC classification number: B82Y10/00 ,  C23C14/042 ,  C23C14/48 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01L21/266 ,  Y10T428/24273

Abstract: Preparing a stencil mask comprising a silicon thin film in which an opening for selectively irradiating charged particles to a semiconductor substrate is provided and whose irradiation surface on which the charged particles are irradiated is implanted with an impurity, and selectively irradiating charged particles to the semiconductor substrate using the stencil mask which is opposingly arranged on the semiconductor substrate.

Abstract translation: 制备包括硅薄膜的模板掩模，其中用于选择性地将带电粒子照射到半导体基板的开口，并且其上照射有带电粒子的照射面被注入杂质，并且将带电粒子选择性地照射到半导体衬底 使用相对设置在半导体衬底上的模板掩模。

公开(公告)号：US20060216875A1

公开(公告)日：2006-09-28

申请号：US11389212

申请日：2006-03-27

Applicant: Takayuki Ito ,  Kouji Matsuo ,  Naoki Tamaoki ,  Yoshinori Honguh ,  Kyoichi Suguro

Inventor： Takayuki Ito ,  Kouji Matsuo ,  Naoki Tamaoki ,  Yoshinori Honguh ,  Kyoichi Suguro

IPC: H01L21/84

CPC classification number: H01L21/324 ,  H01L21/268 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for annealing a semiconductor substrate by light irradiation, includes depositing a translucent film with a predetermined thickness on a semiconductor substrate. The translucent film has a refractive index that is smaller than that of the semiconductor substrate. The thickness is defined by a peak wavelength of the light and the refractive index of the translucent film. The semiconductor substrate is heated in a temperature range of about 300° C. to about 600° C. A surface of the semiconductor substrate is heated with the light which has a pulse width of about 0.1 ms to about 100 ms.

Abstract translation: 通过光照射对半导体衬底进行退火的方法包括在半导体衬底上沉积预定厚度的半透明膜。 半透明膜的折射率小于半导体基板的折射率。 厚度由光的峰值波长和半透明膜的折射率决定。 将半导体衬底在约300℃至约600℃的温度范围内加热。用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面。

公开(公告)号：US20060081893A1

公开(公告)日：2006-04-20

申请号：US11287405

申请日：2005-11-28

Applicant: Kouji Matsuo ,  Kazuaki Nakajima

Inventor： Kouji Matsuo ,  Kazuaki Nakajima

IPC: H01L21/82 ,  H01L31/112

CPC classification number: H01L29/66545 ,  H01L21/28097 ,  H01L21/82345 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0≦y

Abstract translation: 半导体器件包括n型MIS晶体管，其包括第一栅极绝缘膜和第一栅电极，所述第一栅极包括形成在第一栅极绝缘膜上的MSi膜，其中M表示选自钨的金属元素 钼和x大于1，即x> 1; 以及p型MIS晶体管，其包括第二栅极绝缘膜和第二栅电极，所述第二栅电极包括形成在所述第二栅极绝缘膜上的MSi膜，其中y不小于0且小于1， 即0 <= y <1。