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281 条记录 (耗时 0.045 秒)

    Laser fuse with efficient heat dissipation
    61.
    发明申请
    Laser fuse with efficient heat dissipation 有权
    激光熔丝具有高效散热

    公开(公告)号：US20070132059A1

    公开(公告)日：2007-06-14

    申请号：US11299999

    申请日：2005-12-12

    申请人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

    发明人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

    摘要翻译： 提供了具有有效的热路径的半导体结构及其形成方法。 半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。 激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。 保护环通过触点热耦合到半导体衬底。 半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

    Low stress semiconductor device coating and method of forming thereof
    62.
    发明授权
    Low stress semiconductor device coating and method of forming thereof 有权
    低应力半导体器件涂层及其形成方法

    公开(公告)号：US07223630B2

    公开(公告)日：2007-05-29

    申请号：US11004688

    申请日：2004-12-03

    申请人： Shin-Puu Jeng

    发明人： Shin-Puu Jeng

    IPC分类号： H01L21/50 ,  H01L21/48

    CPC分类号： H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low stress, protective coating for a semiconductor device and a method for its manufacture. A preferred embodiment comprises coating the top surface of a semiconductor die with polyimide except for corner regions of the die. Not having corners in the polyimide protective overcoat generally reduces shear stresses in the die. Reducing stress, in turn, generally reduces the occurrence of problems such as fracture, delamination, or cracking within the die. A low stress coating may be particularly advantageous in semiconductor devices having low-k insulating materials, which are generally of low mechanical strength.

    摘要翻译： 用于半导体器件的低应力保护涂层及其制造方法。 一个优选的实施例包括使用聚酰亚胺覆盖半导体管芯的顶表面，除了模具的拐角区域。 在聚酰亚胺保护罩中没有拐角通常会降低模具中的剪切应力。 减少应力又通常减少了在模具内发生诸如断裂，分层或开裂的问题。 低应力涂层在通常具有低机械强度的低k绝缘材料的半导体器件中可能是特别有利的。

    Method for forming a crown capacitor
    66.
    发明授权
    Method for forming a crown capacitor 有权
    形成冠电容器的方法

    公开(公告)号：US6146968A

    公开(公告)日：2000-11-14

    申请号：US209047

    申请日：1998-12-09

    申请人： Yii-Chian Lu ,  Chine-Gie Lou ,  Shin-Puu Jeng

    发明人： Yii-Chian Lu ,  Chine-Gie Lou ,  Shin-Puu Jeng

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

    CPC分类号： H01L28/84 ,  H01L27/10852

    摘要： A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed. The method comprises the steps of: forming a first oxide layer onto the substrate; forming a conductive contact plug in the first oxide layer, the contact plug extending down to the substrate; forming a second oxide layer over the first oxide layer and the contact plug; forming a silicon nitride layer over the second oxide layer; patterning and etching the silicon nitride layer and the second oxide layer to form a trench over the contact plug; forming a layer of rugged insitu doped polysilicon layer over the silicon nitride layer and along the walls and bottom of the trench; depositing a photoresist layer over the rugged insitu doped polysilicon layer and filling the trench; performing a first reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is reached; performing a second reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is removed, the second reactive ion etching step formulated to remove the rugged insitu doped polysilicon layer faster than the photoresist layer; and performing a chemical dry etching step to smooth out the sharp corners of the rugged polysilicon layer.

    摘要翻译： 公开了一种在衬底上形成用于DRAM存储单元的电容器的底部存储节点的方法。 该方法包括以下步骤：在衬底上形成第一氧化物层; 在所述第一氧化物层中形成导电接触插塞，所述接触插头向下延伸到所述衬底; 在所述第一氧化物层和所述接触插塞上形成第二氧化物层; 在所述第二氧化物层上形成氮化硅层; 图案化和蚀刻氮化硅层和第二氧化物层以在接触插塞上形成沟槽; 在氮化硅层上并且沿着沟槽的壁和底部形成一层坚固的本征掺杂多晶硅层; 在坚固的本征掺杂多晶硅层上沉积光致抗蚀剂层并填充沟槽; 执行第一反应离子蚀刻步骤，直到达到位于氮化硅层上的坚固的本征掺杂多晶硅层; 执行第二反应离子蚀刻步骤，直到去除位于氮化硅层上的坚固的本征掺杂多晶硅层，配制第二反应离子蚀刻步骤以比光致抗蚀剂层更快地去除坚固的本征掺杂多晶硅层; 并执行化学干蚀刻步骤，以平滑凹凸多晶硅层的尖角。

    Nanoporous dielectric thin film surface modification
    67.
    发明授权
    Nanoporous dielectric thin film surface modification 失效
    纳米介电薄膜表面改性

    公开(公告)号：US6063714A

    公开(公告)日：2000-05-16

    申请号：US749186

    申请日：1996-11-14

    申请人： Douglas M. Smith ,  Gregory P. Johnston ,  William C. Ackerman ,  Shin-Puu Jeng

    发明人： Douglas M. Smith ,  Gregory P. Johnston ,  William C. Ackerman ,  Shin-Puu Jeng

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/00 ,  B05D3/04

    CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/31695 ,  H01L21/76801

    摘要： This pertains generally to precursors and deposition methods suited to aerogel thin film fabrication of nanoporous dielectrics. A method of forming a nanoporous dielectric on a semiconductor substrate is disclosed. By a method according to the present invention, a precursor sol is applied as a nongelling thin film 14 to a semiconductor substrate 10. This substrate may contain patterned conductors 12, gaps 13, and/or other structures. A portion of the solvent is evaporated from the thin film 14 to produce a reduced thickness film 18. Film 18 is gelled and may be aged. A surface modification agent is introduced to the reaction atmosphere in a vaporish form, e.g., a vapor, mist, aerosol, or similar form. The surface modifier can then diffuse into, condense onto, and/or settle onto the wet gel and then diffuse throughout the thin film. This vaporish introduction of the surface modification agent ensures that there are no strong fluid flows across the wafer that might damage the wet gel. It can also be compatible with standard processing equipment and can potentially be used with other reaction atmosphere controls that reduce premature drying of the gel.

    摘要翻译： 这通常涉及适用于纳米多孔电介质的气凝胶薄膜制造的前体和沉积方法。 公开了一种在半导体衬底上形成纳米多孔电介质的方法。 通过根据本发明的方法，将前体溶胶作为不合格薄膜14施加到半导体衬底10.该衬底可以包含图案化导体12，间隙13和/或其它结构。 溶剂的一部分从薄膜14蒸发以产生厚度减薄的薄膜18.薄膜18胶凝并且可以老化。 将表面改性剂以蒸气形式，例如蒸汽，雾，气溶胶或类似形式引入反应气氛中。 然后，表面改性剂可以扩散进入，冷凝到和/或沉降到湿凝胶上，然后在整个薄膜中扩散。 表面改性剂的蒸发引入确保了晶片上没有强大的流体流动，这可能会损坏湿凝胶。 它也可以与标准的加工设备兼容，并且可以与其他反应气氛控制器一起使用，以减少凝胶的过早干燥。

    Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
    68.
    发明授权
    Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators 失效
    具有嵌入式低介电常数绝缘体的平面化多级互连方案

    公开(公告)号：US5616959A

    公开(公告)日：1997-04-01

    申请号：US473458

    申请日：1995-06-07

    申请人： Shin-Puu Jeng

    发明人： Shin-Puu Jeng

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/28 ,  H01L23/54

    CPC分类号： H01L23/5222 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  H01L2924/12044

    摘要： A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c) . The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).

    摘要翻译： 多级互连结构和方法。 第一多个互连线（14）位于半导体本体（10）的绝缘体层（12）上。 诸如有机聚合物的第一层低介电常数材料（20）填充第一多个互连线（14a-c）之间的区域。 第一层低介电常数材料（20）具有不大于第一多个互连线（14）的高度的高度。 第一层二氧化硅（18）覆盖第一层低介电常数材料（20）和第一多个互连线（14）。

    Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
    69.
    发明授权
    Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators 失效
    具有嵌入式低介电常数绝缘体的平面化多级互连方案

    公开(公告)号：US5486493A

    公开(公告)日：1996-01-23

    申请号：US430095

    申请日：1995-04-26

    申请人： Shin-Puu Jeng

    发明人： Shin-Puu Jeng

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L23/5222 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  H01L2924/12044

    摘要： A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c). The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).

    摘要翻译： 多级互连结构和方法。 第一多个互连线（14）位于半导体本体（10）的绝缘体层（12）上。 诸如有机聚合物的第一层低介电常数材料（20）填充第一多个互连线（14a-c）之间的区域。 第一层低介电常数材料（20）具有不大于第一多个互连线（14）的高度的高度。 第一层二氧化硅（18）覆盖第一层低介电常数材料（20）和第一多个互连线（14）。