公开(公告)号：US11848211B2

公开(公告)日：2023-12-19

申请号：US18111923

申请日：2023-02-21

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tatsuo Shimizu ,  Yukio Nakabayashi ,  Johji Nishio ,  Chiharu Ota ,  Toshihide Ito

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/16 ,  H02P27/06 ,  B61C3/00 ,  B60L50/51 ,  B66B11/04

CPC classification number: H01L21/045 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/046 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  B60L50/51 ,  B60L2210/42 ,  B61C3/00 ,  B66B11/043 ,  H02P27/06

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3 and a carbon concentration at the first position is equal to or less than 1×1018 cm−3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm−3.

公开(公告)号：US20230387267A1

公开(公告)日：2023-11-30

申请号：US18446905

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7856 ,  H01L2029/7858 ,  H01L21/823431 ,  H01L21/0455 ,  H01L29/0669 ,  H01L21/02603

Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

公开(公告)号：US20230386856A1

公开(公告)日：2023-11-30

申请号：US18446415

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien WU

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/04 ,  H01L21/02

CPC classification number: H01L21/32055 ,  H01L29/78672 ,  H01L21/0475 ,  H01L21/02595 ,  H01L21/02683 ,  H01L21/324

Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.

公开(公告)号：US11830925B2

公开(公告)日：2023-11-28

申请号：US17478290

申请日：2021-09-17

Applicant: PARAGRAF LIMITED

Inventor： Thomas James Badcock ,  Robert Wallis ,  Ivor Guiney ,  Simon Thomas

IPC: H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/16 ,  H01L29/76

CPC classification number: H01L29/66045 ,  H01L21/042 ,  H01L29/1606 ,  H01L29/7606 ,  H01L29/7839

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

公开(公告)号：US20230369483A1

公开(公告)日：2023-11-16

申请号：US18183216

申请日：2023-03-14

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Mariko HANASATO ,  Masato NOBORIO ,  Yohei IWAHASHI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/1608 ,  H01L29/0623 ,  H01L29/7813 ,  H01L21/0465 ,  H01L29/66068

Abstract: A semiconductor device includes multiple connecting regions having a second conductivity type and disposed in a cell section and a boundary section. The connecting regions are located between bottom regions and a body region in a thickness direction of a semiconductor layer, in contact with the bottom regions and the body region, and repeatedly arranged at intervals at least in one direction so that a drift region is disposed between the connecting regions.

公开(公告)号：US11817481B2

公开(公告)日：2023-11-14

申请号：US17884559

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  National Taiwan University

Inventor： Hung-Hsiang Cheng ,  Samuel C. Pan

IPC: H01L29/47 ,  H01L29/161 ,  H01L29/872 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L21/324 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L29/161 ,  H01L21/0485 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/28537 ,  H01L21/324 ,  H01L29/16 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/872

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

公开(公告)号：US20230361210A1

公开(公告)日：2023-11-09

申请号：US18353109

申请日：2023-07-17

Applicant: ROHM CO., LTD.

Inventor： Takui SAKAGUCHI ,  Masatoshi AKETA ,  Yuki NAKANO

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7806 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

公开(公告)号：US20230361169A1

公开(公告)日：2023-11-09

申请号：US17878208

申请日：2022-08-01

Applicant: National Yang Ming Chiao Tung University

Inventor： Bing-Yue Tsui ,  Yu-Chia Tsui ,  Jui-Cheng Wang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04

CPC classification number: H01L29/0619 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/7811

Abstract: A method for stabilizing breakdown voltages of floating guard ring, applicable to a high power device, is provided. The high power device has a semiconductor substrate layer, and at least one floating guard ring is formed at its termination. The method includes sequentially providing a pad oxide layer and barrier layer on an upper surface of the high power device to expose the floating guard ring, and then performing an ion implantation step. After removing the pad oxide layer and barrier layer, grow a field oxide layer, such that a defect layer is formed underneath. By employing the formed defect layer, the present invention achieves to control an interface potential level between the field oxide layer and the semiconductor substrate layer fixed at a certain potential value, without being affected by charges in the oxide layer or metal across over it, thereby stabilizing breakdown voltages of floating guard ring.

公开(公告)号：US11804520B2

公开(公告)日：2023-10-31

申请号：US17464296

申请日：2021-09-01

Applicant: ROHM CO., LTD.

Inventor： Yuki Nakano ,  Ryota Nakamura

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16 ,  H01L27/088 ,  H01L21/04 ,  H01L29/04 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/063 ,  H01L21/046 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7811

Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.

公开(公告)号：US20230335430A1

公开(公告)日：2023-10-19

申请号：US17809092

申请日：2022-06-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Guangsu Shao ,  Deyuan Xiao ,  Yunsong Qiu ,  Youming Liu ,  Yi Jiang ,  Xingsong Su ,  Yuhan Zhu

IPC: H01L21/762 ,  H01L21/04 ,  H01L21/311

CPC classification number: H01L21/76205 ,  H01L21/041 ,  H01L21/042 ,  H01L21/311

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.