公开(公告)号：US20170012115A1

公开(公告)日：2017-01-12

申请号：US15115999

申请日：2015-02-03

Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

Inventor： Seong Jin KOH ,  Pradeep BHADRACHALAM ,  Liang-Chieh MA

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/12 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66977 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0895 ,  H01L29/122 ,  H01L29/127 ,  H01L29/24 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L29/7827 ,  H01L29/882 ,  Y10S977/774 ,  Y10S977/937

Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Abstract translation: 经过能量过滤的冷电子器件使用通过隧穿势垒导带的带状弯曲形成的量子阱或量子点的离散能级的电子能量过滤。 这些器件在室温下可获得小于或等于45K的低有效电子温度，陡峭的电流接通/关断能力，室温下的陡度小于或等于10 mV /十倍，亚阈值摆幅 在室温下小于或等于10mV /十倍，和/或小于或等于0.1V的电源电压。

公开(公告)号：US09029936B2

公开(公告)日：2015-05-12

申请号：US13708677

申请日：2012-12-07

Applicant: SanDisk Technologies, Inc.

Inventor： Vinod Purayath ,  George Samachisa ,  George Matamis ,  James Kai ,  Yuan Zhang

IPC: H01L29/792 ,  H01L29/76 ,  H01L29/788 ,  H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/937 ,  Y10S977/938 ,  Y10S977/943

Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.

Abstract translation: 存储器件包括半导体通道，位于半导体通道上方的隧道电介质层，包括位于隧道介电层上方的多个导电纳米点的第一电荷阱，位于纳米点上方的介电分离层，第二电荷阱， 位于分离层上方的连续金属层，位于第二电荷阱上方的阻挡电介质，以及位于阻挡电介质上方的控制栅极。

公开(公告)号：US08232561B2

公开(公告)日：2012-07-31

申请号：US12677457

申请日：2008-09-10

Applicant: Andrew Gabriel Rinzler ,  Bo Liu ,  Mitchell Austin McCarthy ,  John Robert Reynolds ,  Franky So

Inventor： Andrew Gabriel Rinzler ,  Bo Liu ,  Mitchell Austin McCarthy ,  John Robert Reynolds ,  Franky So

IPC: H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L27/15 ,  H01L29/18 ,  H01L31/12 ,  H01L33/00 ,  H01L29/26

CPC classification number: H01L51/5296 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0048 ,  H01L51/0558 ,  H01L51/057 ,  H01L51/102 ,  H01L51/5203 ,  Y10S977/701 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/767 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

Abstract translation: 本发明的实施例涉及作为发光晶体管的垂直场效应晶体管。 发光晶体管包括用于提供栅极场的栅电极，包括用于注入电荷的稀释纳米管网络的第一电极，用于注入互补电荷的第二电极和设置在纳米管网络之间的电致发光半导体层和电子注入 层。 电荷注入由栅极场调制。 空穴和电子结合形成光子，从而使电致发光半导体层发射可见光。 在本发明的其它实施例中，采用包括具有低密度状态的导电材料的电极的垂直场效应晶体管，使得晶体管接触势垒调制包括具有低密度状态的电极之间的肖特基接触的势垒高度降低，以及 相邻的半导体通过费米能级移位。

公开(公告)号：US08143658B2

公开(公告)日：2012-03-27

申请号：US12450373

申请日：2008-03-26

Applicant: Lars Samuelson ,  Claes Thelander

Inventor： Lars Samuelson ,  Claes Thelander

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/16 ,  H01L27/11521 ,  H01L27/1156 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66477 ,  H01L29/7888 ,  H01L29/792 ,  H01L29/7926 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.

Abstract translation: 本发明涉及一种用于电荷存储的纳米结构装置。 特别地，本发明涉及一种可用于存储器应用的电荷存储装置。 根据本发明，该装置包括第一纳米线，其具有围绕其一部分长度布置的第一卷绕栅极和连接到一端的电荷存储端子，以及第二纳米线，其具有围绕其长度的一部分布置的第二卷绕栅极。 电荷存储端子连接到第二卷绕栅极，由此存储在电荷存储端子上的电荷可以影响第二纳米线中的电流。 电流可以与写入（充电）或未写入（无电荷）状态有关，因此建立了记忆功能。

公开(公告)号：US08124961B2

公开(公告)日：2012-02-28

申请号：US13152900

申请日：2011-06-03

Applicant: Sung-Dae Suk ,  Kyoung-Hwan Yeo ,  Ming Li ,  Yun-Young Yeoh

Inventor： Sung-Dae Suk ,  Kyoung-Hwan Yeo ,  Ming Li ,  Yun-Young Yeoh

IPC: H01L29/06 ,  H01L31/00 ,  H01L21/02

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S438/962 ,  Y10S977/937 ,  Y10S977/938

Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract translation: 单电子晶体管包括分离在衬底上的源极/漏极层，连接源极/漏极层的至少一个纳米线沟道，纳米线沟道中的多个氧化物沟道区域，绝缘纳米线的至少一部分的氧化物沟道区域 通道，在由多个氧化物通道区域绝缘的纳米线通道的部分中的量子点和围绕量子点的栅电极。

公开(公告)号：US20100330751A1

公开(公告)日：2010-12-30

申请号：US12874146

申请日：2010-09-01

Applicant: Jung Bum Choi ,  Seung Jun Shin

Inventor： Jung Bum Choi ,  Seung Jun Shin

IPC: H01L21/335

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/937

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract translation: 本发明涉及在室温下工作的单电子晶体管（SET）及其制造方法，具体涉及在室温下工作的单电子晶体管及其制造方法，其为 能够最小化栅极电压对隧道势垒的影响并有效地控制量子点（QD）的电位，通过使用沟槽纳米线结构形成量子点并形成栅极围绕量子包裹大部分 点。

公开(公告)号：US07629244B2

公开(公告)日：2009-12-08

申请号：US11491281

申请日：2006-07-24

Applicant: Soo-doo Chae ,  Chung-woo Kim ,  Ju-hyung Kim

Inventor： Soo-doo Chae ,  Chung-woo Kim ,  Ju-hyung Kim

IPC: H01L21/4763

CPC classification number: B82Y10/00 ,  H01L29/7888 ,  Y10S977/937 ,  Y10S977/938

Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

Abstract translation: 公开了具有记忆功能的单电子晶体管及其制造方法。 在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜 在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱 层和至少两个陷阱层之间的隧道膜。 由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

公开(公告)号：US20080012003A1

公开(公告)日：2008-01-17

申请号：US11898116

申请日：2007-09-10

Applicant: Haizhi Song

Inventor： Haizhi Song

IPC: H01L29/06

CPC classification number: H01L29/127 ,  B82Y10/00 ,  H01L29/205 ,  H01L33/06 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/933 ,  Y10S977/937

Abstract: A quantum dot (22) is formed on a GaAs substrate (20). In the quantum dot (22), a single electron exists. A cap layer (26) is formed on a surrounding area of the quantum dot (22), and a barrier layer (28) is formed thereon. A quantum dot (30) for detection is formed on the barrier layer (28). Then, a cap layer (34) covering the quantum dot (30) and the like is formed.

Abstract translation: 在GaAs衬底（20）上形成量子点（22）。 在量子点（22）中，存在单个电子。 在量子点（22）的周围区域上形成有盖层（26），在其上形成阻挡层（28）。 用于检测的量子点（30）形成在阻挡层（28）上。 然后，形成覆盖量子点（30）的盖层（34）等。

公开(公告)号：US20070267735A1

公开(公告)日：2007-11-22

申请号：US11706347

申请日：2007-02-15

Applicant: Yuji Awano ,  Masataka Mizukoshi ,  Taisuke Iwai ,  Tomoji Nakamura

Inventor： Yuji Awano ,  Masataka Mizukoshi ,  Taisuke Iwai ,  Tomoji Nakamura

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/6835 ,  H01L23/49877 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/72 ,  H01L24/73 ,  H01L24/90 ,  H01L24/91 ,  H01L2224/03505 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81901 ,  H01L2224/81904 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  Y10S977/72 ,  Y10S977/721 ,  Y10S977/722 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/766 ,  Y10S977/784 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938 ,  Y10S977/963 ,  H01L2924/00 ,  H01L2224/72

Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.

Abstract translation: 多个导电焊盘（2）形成在安装板的安装表面上。 当主表面朝向安装板时，导电焊盘（11）在与安装板的导电焊盘相对应的位置处形成在半导体芯片（10）的主表面上。 多个导电纳米管（12）从安装板和半导体芯片之一的导电焊盘延伸。 按压机构（3）将半导体芯片压靠在安装基板上，并将半导体芯片的位置限制在安装面上，以将半导体芯片安装在安装基板上，导电性纳米管的尖端与 不形成导电纳米管的相应的导电焊盘。

公开(公告)号：US20050153484A1

公开(公告)日：2005-07-14

申请号：US10982730

申请日：2004-11-03

Applicant: Christoph Wasshuber

Inventor： Christoph Wasshuber

IPC: H01L29/76 ,  H01L21/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  G11C2213/17 ,  G11C2216/08 ,  H01L29/7613 ,  Y10S977/937

Abstract: The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (110) located over a substrate (115) and a quantum island (120) situated between the source and drain (105, 110), to form tunnel junctions (125, 130) between the source and drain (105, 110). The device (100) further includes a movable electrode (135) located adjacent the quantum island (120) and a displaceable dielectric (140) located between the moveable electrode (135) and the quantum island (120). The present invention also includes a method of fabricating a single-electron device (200), and a transistor circuit (300) that include a single-electron device (310).

Abstract translation: 本发明提供一种单电子晶体管器件（100）。 设备（100）包括位于衬底（115）上的源极（105）和漏极（110）以及位于源极和漏极（105,110）之间的量子岛（120），以形成隧道结（125,130） ）在源极和漏极（105,110）之间。 装置（100）还包括位于量子岛（120）附近的可移动电极（135）和位于可动电极（135）和量子岛（120）之间的位移电介质（140）。 本发明还包括制造单电子器件（200）的方法和包括单电子器件（310）的晶体管电路（300）。