公开(公告)号：US20170345898A1

公开(公告)日：2017-11-30

申请号：US15536706

申请日：2015-12-01

Applicant: Nokia Technologies Oy

Inventor： Michael ASTLEY

IPC: H01L29/08 ,  C01B21/064 ,  C01B32/182 ,  H01L29/20 ,  H01L29/16 ,  H01L29/73 ,  H01L29/76 ,  B82Y10/00 ,  H01L29/88

CPC classification number: H01L29/0895 ,  B82Y10/00 ,  C01B21/064 ,  C01B32/182 ,  C01P2006/40 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/7311 ,  H01L29/7613 ,  H01L29/882 ,  Y10S977/734 ,  Y10S977/831 ,  Y10S977/937

Abstract: An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).

公开(公告)号：US20140001535A1

公开(公告)日：2014-01-02

申请号：US13708677

申请日：2012-12-07

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Vinod Purayath ,  George Samachisa ,  George Matamis ,  James Kai ,  Yuan Zhang

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/937 ,  Y10S977/938 ,  Y10S977/943

Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.

Abstract translation: 存储器件包括半导体通道，位于半导体通道上方的隧道电介质层，包括位于隧道介电层上方的多个导电纳米点的第一电荷阱，位于纳米点上方的介电分离层，第二电荷阱， 位于分离层上方的连续金属层，位于第二电荷阱上方的阻挡电介质，以及位于阻挡电介质上方的控制栅极。

公开(公告)号：US08564048B2

公开(公告)日：2013-10-22

申请号：US13528953

申请日：2012-06-21

Applicant: Andrew Gabriel Rinzler ,  Bo Liu ,  Mitchell Austin McCarthy ,  John Robert Reynolds ,  Franky So

Inventor： Andrew Gabriel Rinzler ,  Bo Liu ,  Mitchell Austin McCarthy ,  John Robert Reynolds ,  Franky So

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L51/5296 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0048 ,  H01L51/0558 ,  H01L51/057 ,  H01L51/102 ,  H01L51/5203 ,  Y10S977/701 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/767 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: Embodiments of the invention relate to field effect transistors. The field effect transistor includes a gate electrode for providing a gate field, a first electrode including a conductive material having a low carrier density and a low density of electronic states, a second electrode, and a semiconductor. Contact barrier modulation includes barrier height lowering of a Schottky contact between the first electrode and the semiconductor. In some embodiments of the invention, a vertical field effect transistor employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

Abstract translation: 本发明的实施例涉及场效应晶体管。 场效应晶体管包括用于提供栅极场的栅电极，包括具有低载流子密度和低密度电子状态的导电材料的第一电极，第二电极和半导体。 接触势垒调制包括第一电极和半导体之间的肖特基接触的势垒高度降低。 在本发明的一些实施例中，垂直场效应晶体管采用包括具有低密度状态的导电材料的电极，使得晶体管接触势垒调制包括具有低密度状态的电极之间的肖特基接触的势垒高度降低;以及 相邻的半导体通过费米能级移位。

公开(公告)号：US08232165B2

公开(公告)日：2012-07-31

申请号：US13184004

申请日：2011-07-15

Applicant: Dureseti Chidambarrao ,  Lidija Sekaric

Inventor： Dureseti Chidambarrao ,  Lidija Sekaric

IPC: H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78687 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/825 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract translation: 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的核缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。

公开(公告)号：US20110275198A1

公开(公告)日：2011-11-10

申请号：US13184004

申请日：2011-07-15

Applicant: Dureseti Chidambarrao ,  Lidija Sekaric

Inventor： Dureseti Chidambarrao ,  Lidija Sekaric

IPC: H01L21/20 ,  B82Y40/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78687 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/825 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract translation: 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的芯缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。

公开(公告)号：US08026508B2

公开(公告)日：2011-09-27

申请号：US12498402

申请日：2009-07-07

Applicant: Myung-Sim Jun ,  Moon-Gyu Jang ,  Tae-Gon Noh ,  Tae-Moon Roh

Inventor： Myung-Sim Jun ,  Moon-Gyu Jang ,  Tae-Gon Noh ,  Tae-Moon Roh

IPC: H01L33/00 ,  H01L29/78

CPC classification number: H01L29/122 ,  B82Y10/00 ,  H01L31/113 ,  Y10S977/937 ,  Y10S977/953

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：包括第一量子点的单个电子盒，第一量子点上的电荷存储栅极和电荷存储栅极上的第一栅电极，电荷存储栅极与第一量子点交换电荷，第一量子点 栅电极调整第一量子点的电位; 以及包括第一量子点下方的第二量子点的单电子晶体管，位于第二量子点下方的源极，漏极和第二栅电极，第二量子点电容耦合到第一量子点，源极与第一量子点接触 所述第二量子点的所述漏极与所述一侧面对的另一侧接触，所述第二栅电极调整所述第二量子点的电位。

公开(公告)号：US20110049473A1

公开(公告)日：2011-03-03

申请号：US12549741

申请日：2009-08-28

Applicant: Dureseti Chidambarrao ,  Lidija Sekaric

Inventor： Dureseti Chidambarrao ,  Lidija Sekaric

IPC: H01L29/12 ,  H01L21/31

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78687 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/825 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract translation: 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的芯缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。

公开(公告)号：US20100155703A1

公开(公告)日：2010-06-24

申请号：US12498402

申请日：2009-07-07

Applicant: Myung-Sim JUN ,  Moon-Gyu JANG ,  Tae-Gon NOH ,  Tae-Moon ROH

Inventor： Myung-Sim JUN ,  Moon-Gyu JANG ,  Tae-Gon NOH ,  Tae-Moon ROH

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/122 ,  B82Y10/00 ,  H01L31/113 ,  Y10S977/937 ,  Y10S977/953

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：包括第一量子点的单个电子盒，第一量子点上的电荷存储栅极和电荷存储栅极上的第一栅电极，电荷存储栅极与第一量子点交换电荷，第一量子点 栅电极调整第一量子点的电位; 以及包括第一量子点下方的第二量子点的单电子晶体管，位于第二量子点下方的源极，漏极和第二栅电极，第二量子点电容耦合到第一量子点，源极与第一量子点接触 所述第二量子点的所述漏极与所述一侧面对的另一侧接触，所述第二栅电极调整所述第二量子点的电位。

公开(公告)号：US07498084B2

公开(公告)日：2009-03-03

申请号：US10488478

申请日：2002-08-29

Applicant: Motohiro Yamahara ,  Masanobu Mizusaki

Inventor： Motohiro Yamahara ,  Masanobu Mizusaki

IPC: B32B9/04

CPC classification number: H01L51/0095 ,  C08G83/005 ,  C08L101/005 ,  H01L27/3244 ,  H01L51/0053 ,  H01L51/0076 ,  H01L51/0077 ,  H01L51/0545 ,  H01L51/42 ,  H01L51/5012 ,  H01L51/5048 ,  H01L2251/308 ,  Y10S977/754 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938 ,  Y10T428/31504

Abstract: A functional device includes a pair of electrodes 1 and 4 and a macromolecular structure including a hole-conducting layer 5 and an electron-conducting layer 2. The macromolecular structure includes a first hyperbranched macromolecule and a second hyperbranched macromolecule, at least one of the first hyperbranched macromolecule and the second hyperbranched macromolecule has a hole conductivity or an electron conductivity, one of the hole-conducting layer and the electron-conducting layer includes one of the first hyperbranched macromolecule and the second hyperbranched macromolecule, and the macromolecular structure has a self-assembled structure formed by a non-covalent interaction via the first hyperbranched macromolecule or the second hyperbranched macromolecule in at least one of the hole-conducting layer, the electron-conducting layer and the interface between the hole-conducting layer and the electron-conducting layer.

Abstract translation: 功能器件包括一对电极1和4以及包括空穴传导层5和电子传导层2的大分子结构。大分子结构包括第一超支化高分子和第二超支化高分子，至少一个第一 超支化高分子和第二超支化高分子具有空穴导电性或电子传导性，空穴传导层和电子传导层之一包括第一超支化高分子和第二超支化高分子之一，并且大分子结构具有自分支结构， 通过第一超支化高分子或第二超支化高分子在空穴传导层，电子传导层和空穴传导层和电子传导层之间的界面中的至少一个中通过非共价相互作用形成的组装结构 。

公开(公告)号：US20080246021A1

公开(公告)日：2008-10-09

申请号：US11905758

申请日：2007-10-03

Applicant: Sung-Dae Suk ,  Kyoung-Hwan Yeo ,  Ming Li ,  Yun-Young Yeoh

Inventor： Sung-Dae Suk ,  Kyoung-Hwan Yeo ,  Ming Li ,  Yun-Young Yeoh

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S438/962 ,  Y10S977/937 ,  Y10S977/938

Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract translation: 单电子晶体管包括分离在衬底上的源极/漏极层，连接源极/漏极层的至少一个纳米线沟道，纳米线沟道中的多个氧化物沟道区域，绝缘纳米线的至少一部分的氧化物沟道区域 通道，在由多个氧化物通道区域绝缘的纳米线通道的部分中的量子点和围绕量子点的栅电极。