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    Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
    1.
    发明授权
    Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors 有权
    具有用于外围晶体管的外延半导体基座的三维存储器件

    公开(公告)号：US09543318B1

    公开(公告)日：2017-01-10

    申请号：US14832579

    申请日：2015-08-21

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Zhenyu Lu ,  Daxin Mao ,  Koji Miyata ,  Junichi Ariyoshi ,  Johann Alsmeier ,  George Matamis ,  Wenguang Shi ,  Jiyin Xu ,  Xiaolong Hu

    IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

    Abstract: An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.

    Abstract translation: 在衬底上形成交替堆叠的绝缘体层和间隔物层。 步进的表面形成在接触区域中，接触通孔结构将随后形成。 外延半导体基座可以通过在形成台阶表面之后并且在形成存储器开口之前执行的单个外延沉积工艺形成，或者在形成存储器开口之前执行的第一外延沉积工艺和第二外延 在形成存储器开口之后执行沉积工艺。 外延半导体基座可以具有位于交替堆叠的最上表面上方的顶表面。 间隔材料层由导电层形成或可以被导电层代替。 可以随后形成通过结构的背面接触。

    Ruthenium nucleation layer for control gate electrodes in a memory structure
    3.
    发明授权
    Ruthenium nucleation layer for control gate electrodes in a memory structure 有权
    钌成核层，用于存储结构中的控制栅电极

    公开(公告)号：US09496419B2

    公开(公告)日：2016-11-15

    申请号：US14553124

    申请日：2014-11-25

    Applicant: SanDisk Technologies, Inc.

    Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Sateesh Koka ,  George Matamis

    IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/7889 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a ruthenium portion can be formed in each backside recess, and a polycrystalline conductive material portion can be formed on each ruthenium portion. Each ruthenium portion can be employed in lieu of a tungsten seed layer to function as a lower resistivity seed layer that enables subsequent deposition of a polycrystalline conductive material. The resulting electrically conductive lines can have a lower resistivity than conductive lines of comparable dimensions that employ tungsten seed layers.

    Abstract translation: 可以在每个存储器开口内形成记忆膜和半导体通道，该存储器开口延伸穿过包括交替的多个绝缘体层和牺牲材料层的堆叠。 在通过去除对绝缘体层选择性的牺牲材料层形成后侧凹槽之后，可以在每个后侧凹部中形成钌部分，并且可以在每个钌部分上形成多晶导电材料部分。 可以使用每个钌部分代替钨种子层，以用作能够随后沉积多晶导电材料的较低电阻率种子层。 所得到的导电线可以具有比使用钨种子层的相当尺寸的导线更低的电阻率。

    Fluorine-free word lines for three-dimensional memory devices
    6.
    发明授权
    Fluorine-free word lines for three-dimensional memory devices 有权
    无氟字线用于三维存储器件

    公开(公告)号：US09397046B1

    公开(公告)日：2016-07-19

    申请号：US14699749

    申请日：2015-04-29

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Sateesh Koka ,  George Matamis

    IPC: H01L29/76 ,  H01L23/532 ,  H01L27/115 ,  H01L23/535 ,  H01L21/768

    CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76877 ,  H01L23/53257 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Fluorine-induced formation of voids and electrical shorts can be avoided by forming fluorine-free metal lines. Specifically, control gate electrodes of a three-dimensional memory device can be formed employing fluorine-free deposition processes. Fluorine-free tungsten nitride can be deposited as a metallic barrier liner employing atomic layer deposition. Fluorine-free tungsten nucleation layer can be subsequently deposited. Fluorine-free tungsten fill process can be employed to form the control gate electrodes. The fluorine-free control gate electrodes do not include fluorine therein, and thus, circumvents yield and reliability issues associated with residual fluorine that are present in fluorine-containing metal lines.

    Abstract translation: 通过形成无氟金属线可以避免氟引起的空隙形成和电短路。 具体地，可以使用无氟沉积工艺形成三维存储器件的控制栅电极。 可以使用原子层沉积作为金属阻挡层而沉积无氟氮化钨。 随后可以沉积无氟钨成核层。 可以使用无氟钨填充工艺来形成控制栅电极。 无氟控制栅电极中不含氟，因此，避免了存在于含氟金属线中的残留氟的产率和可靠性问题。

    Methods of selective removal of blocking dielectric in NAND memory strings
    9.
    发明授权
    Methods of selective removal of blocking dielectric in NAND memory strings 有权
    选择性去除NAND存储器串中的阻塞电介质的方法

    公开(公告)号：US09230974B1

    公开(公告)日：2016-01-05

    申请号：US14468743

    申请日：2014-08-26

    Applicant: SanDisk Technologies, Inc.

    Inventor： Jayavel Pachamuthu ,  Johann Alsmeier ,  George Matamis ,  Henry Chien

    IPC: H01L29/76 ,  H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/1157

    Abstract: Methods of making a monolithic three dimensional NAND string may enable selective removal of a blocking dielectric material, such as aluminum oxide, without otherwise damaging the device. Blocking dielectric may be selectively removed from the back side (e.g., slit trench) and/or front side (e.g., memory opening) of the NAND string. Also disclosed are NAND strings made in accordance with the embodiment methods.

    Abstract translation: 制造单片三维NAND串的方法可以使得能够选择性地去除阻挡电介质材料，例如氧化铝，而不会以其他方式损坏器件。 可以从NAND串的背面（例如，狭缝沟槽）和/或前侧（例如，存储器开口）选择性地去除阻塞电介质。 还公开了根据实施方式制造的NAND串。

    METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES
    10.
    发明申请
    METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES 有权
    制造三维NAND器件的方法

    公开(公告)号：US20150380423A1

    公开(公告)日：2015-12-31

    申请号：US14319283

    申请日：2014-06-30

    Applicant: SanDisk Technologies, Inc.

    Inventor： Senaka Krishna Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Yao-Sheng Lee ,  Johann Alsmeier ,  George Matamis

    IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28

    CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/4916

    Abstract: A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.

    Abstract translation: 制造单片三维NAND串的方法包括在衬底的主表面上提供交替的第一材料层和第二材料层的第一堆叠。 第一材料层包括第一氧化硅层，第二材料层包括第二氧化硅层，并且当暴露于相同的蚀刻介质时，第一氧化硅层具有与第二氧化硅不同的蚀刻速率。 第一堆叠包括背侧开口，前侧开口，以及至少一部分浮栅层，隧道电介质和位于前侧开口中的半导体通道。 该方法还包括通过后侧开口选择性地去除第一材料层，以在相邻的第二材料层之间形成背侧控制栅极凹部。

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