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    Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels
    3.
    发明授权
    Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels 有权
    具有垂直通道的硅/氧化物/氮化物/硅非易失性存储器

    公开(公告)号：US07439574B2

    公开(公告)日：2008-10-21

    申请号：US10460673

    申请日：2003-06-13

    申请人： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

    发明人： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7926 ,  G11C11/5628 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7923

    摘要： Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

    摘要翻译： 提供了硅/氧化物/氮化物/氧化物/硅（SONOS）存储器，其制造方法和存储器编程方法。 SONOS存储器包括基板; 堆叠在所述基板上的第一绝缘层; 半导体层，其在预定形状的第一绝缘层上图案化，包括以预定间隔隔开的源极和漏极; 位于源极和漏极之间的半导体层上的第二绝缘层; 存储层，其沉积在源极和漏极之间的半导体层的一部分的侧面上，并且沉积在包括电子传输沟道和电子存储层的第二绝缘层的侧面和上表面上; 以及沉积在存储层的表面上用于控制存储层中电子转移的栅电极。 编程方法可以提供大容量，稳定的多级存储器。

    Nonvolatile memory device and method of fabricating the same
    5.
    发明申请
    Nonvolatile memory device and method of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20080087940A1

    公开(公告)日：2008-04-17

    申请号：US11589994

    申请日：2006-10-31

    申请人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

    发明人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

    IPC分类号： H01L29/792 ,  H01L21/8238

    CPC分类号： H01L29/792 ,  H01L29/66833 ,  H01L29/7926

    摘要： A nonvolatile memory device, includes a semiconductor substrate having a bottom part, a second vertical part positioned vertically on the bottom part, and a first vertical part having a width smaller than a width of the second vertical part and positioned on the second vertical part to have a boundary step therebetween; a charge trap layer disposed on a lateral surface of the first vertical part and on an upper surface of the boundary step; and a control gate electrode disposed on an upper surface of the bottom part and on lateral surfaces of the second vertical part and the charge trap layer.

    摘要翻译： 一种非易失性存储器件，包括：半导体衬底，具有底部;垂直于第二垂直方向的底部;以及第一垂直部分，其宽度小于第二垂直部分的宽度，并且位于第二垂直部分上， 在其间具有边界步骤; 电荷陷阱层，设置在所述第一垂直部分的侧表面和所述边界台阶的上表面上; 以及设置在所述底部的上表面和所述第二垂直部分和所述电荷陷阱层的侧表面上的控制栅电极。

    Memory devices including barrier layers and methods of manufacturing the same
    6.
    发明授权
    Memory devices including barrier layers and methods of manufacturing the same 有权
    存储器件包括阻挡层及其制造方法

    公开(公告)号：US07358137B2

    公开(公告)日：2008-04-15

    申请号：US11245426

    申请日：2005-10-07

    申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

    发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  H01L29/513 ,  H01L29/7881

    摘要： Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may be formed of at least two layers. The at least two layers may have different bandgap energies.

    摘要翻译： 提供了存储器件及其制造方法。 存储器件可以包括衬底，源极区域和漏极区域以及栅极结构。 栅极结构可以与源极和漏极区域接触，并且可以包括阻挡层。 阻挡层可以由至少两层形成。 至少两层可能具有不同的带隙能量。

    Method of erasing data from SONOS memory device
    7.
    发明申请
    Method of erasing data from SONOS memory device 审中-公开
    从SONOS存储器件擦除数据的方法

    公开(公告)号：US20070138541A1

    公开(公告)日：2007-06-21

    申请号：US11702064

    申请日：2007-02-05

    申请人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

    发明人： Soo-doo Chae ,  Chung-woo Kim ,  Jo-won Lee ,  Moon-kyung Kim

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  G11C16/0466

    摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

    摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。 第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。 可以在栅电极和捕获膜之间设置阻挡膜。 第二标志的电荷载体可能是热孔。 这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

    Nonvolatile memory device and method of manufacturing the same
    8.
    发明申请
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20060273377A1

    公开(公告)日：2006-12-07

    申请号：US11504702

    申请日：2006-08-16

    申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    IPC分类号： H01L29/788

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

    Non-volatile semiconductor memory device with alternative metal gate material
    9.
    发明申请
    Non-volatile semiconductor memory device with alternative metal gate material 有权
    具有替代金属栅极材料的非易失性半导体存储器件

    公开(公告)号：US20060118858A1

    公开(公告)日：2006-06-08

    申请号：US11246114

    申请日：2005-10-11

    申请人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

    发明人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

    摘要翻译： 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

    Method of operating a SONOS memory device
    10.
    发明授权
    Method of operating a SONOS memory device 有权
    操作SONOS存储器件的方法

    公开(公告)号：US07825459B2

    公开(公告)日：2010-11-02

    申请号：US12453147

    申请日：2009-04-30

    申请人： Ju-hyung Kim ,  Chung-woo Kim ,  Soo-doo Chae ,  Youn-seok Jeong

    发明人： Ju-hyung Kim ,  Chung-woo Kim ,  Soo-doo Chae ,  Youn-seok Jeong

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

    摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

    摘要翻译： 氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。 栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。 纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。 存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。