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    Memory elements with elevated control signal levels for integrated circuits
    52.
    发明授权
    Memory elements with elevated control signal levels for integrated circuits 有权
    具有升高的集成电路控制信号电平的存储器元件

    公开(公告)号：US09245592B2

    公开(公告)日：2016-01-26

    申请号：US13204466

    申请日：2011-08-05

    Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    IPC: G11C5/14 ,  G11C11/413 ,  G05F1/46 ,  H03K19/177

    CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

    Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

    Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

    Bypassable clocked storage circuitry for dynamic voltage-frequency scaling
    53.
    发明授权
    Bypassable clocked storage circuitry for dynamic voltage-frequency scaling 有权
    用于动态电压 - 频率缩放的可绕过时钟的存储电路

    公开(公告)号：US09065440B2

    公开(公告)日：2015-06-23

    申请号：US13754579

    申请日：2013-01-30

    Applicant: Altera Corporation

    Inventor： Jeffrey Christopher Chromczak

    IPC: G06F1/10 ,  H03K19/177 ,  H03K19/0175 ,  H03K19/00

    CPC classification number: H03K19/0175 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3296 ,  H03K19/00 ,  H03K19/17792 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.

    Abstract translation: 提供具有顺序逻辑电路的集成电路。 顺序逻辑电路可以包括耦合在速度关键输入端和速度关键输出端之间的可连接时钟存储元件链。 组合逻辑电路可以插入在链中的每个相邻的可旁路计时存储元件对之间。 动态电压 - 频率缩放（DVFS）控制电路可以向组合逻辑电路提供可调节的电源电压，并且可以提供可调节的时钟信号以控制时钟存储元件。 DVFS控制电路可以用于选择性地启用至少一些可旁路时钟存储元件，同时禁用其他可旁路的时钟存储元件，使得可以在保持相同的工作频率的同时降低电源电压。 可以调整电源电压和时钟信号的频率以提供所需的电压 - 频率折衷。

    APPARATUS AND METHOD FOR CORRECTING OUTPUT SIGNAL OF FPGA-BASED MEMORY TEST DEVICE
    54.
    发明申请
    APPARATUS AND METHOD FOR CORRECTING OUTPUT SIGNAL OF FPGA-BASED MEMORY TEST DEVICE 有权
    用于校正基于FPGA的存储器测试设备的输出信号的装置和方法

    公开(公告)号：US20150035561A1

    公开(公告)日：2015-02-05

    申请号：US14446482

    申请日：2014-07-30

    Applicant: UNITEST INC.

    Inventor： Ho Sang YOU

    IPC: H03K19/003 ,  H03K19/177

    CPC classification number: H03K19/00369 ,  H03K19/17792

    Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

    Abstract translation: 用于校正基于FPGA的存储器测试装置的输出信号的装置和方法包括用于输出具有不同相位的时钟信号的时钟发生器; 以及模式发生器，用于响应于从时钟发生器输入的时钟信号输出地址信号，数据信号和时钟信号，以及使用用于定时测量的触发器来校正每个输出信号的定时。 其中通过模式发生器的地址信号，数据信号和时钟信号用诸如FPGA的可编程逻辑来实现，从而在不使用外部延迟装置的情况下缩短校正时间，并且提高了 信号用于记忆测试，最终提高记忆测试仪的性能（精度）。

    Programmable integrated circuit and method of asynchronously routing data in an integrated circuit
    58.
    发明授权
    Programmable integrated circuit and method of asynchronously routing data in an integrated circuit 有权
    可编程集成电路和集成电路中异步路由数据的方法

    公开(公告)号：US08358148B1

    公开(公告)日：2013-01-22

    申请号：US12896720

    申请日：2010-10-01

    Applicant: Alireza S. Kaviani

    Inventor： Alireza S. Kaviani

    IPC: H03K19/173

    CPC classification number: H03K19/1736 ,  H03K19/1774 ,  H03K19/17792

    Abstract: A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a matrix of circuit blocks, each circuit block of the matrix of circuit blocks comprising configurable blocks; and a routing network coupled to the matrix of circuit blocks, the routing network having a plurality of programmable interconnect points comprising buffers enabling asynchronous communication. A method of asynchronously routing data in an integrated circuit is also disclosed.

    Abstract translation: 公开了一种可编程集成电路。 可编程集成电路包括电路块矩阵，电路块矩阵的每个电路块包括可配置块; 以及耦合到所述电路块的矩阵的路由网络，所述路由网络具有多个可编程互连点，其包括启用异步通信的缓冲器。 还公开了一种在集成电路中异步路由数据的方法。

    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS
    59.
    发明申请
    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开
    具有可编程逻辑器件集成电路的高电压电平的易失性存储器元件

    公开(公告)号：US20110285422A1

    公开(公告)日：2011-11-24

    申请号：US13204466

    申请日：2011-08-05

    Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

    IPC: H03K19/173

    CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

    Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

    Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

    Programmable logic block of FPGA using phase-change memory device
    60.
    发明授权
    Programmable logic block of FPGA using phase-change memory device 有权
    使用相变存储器件的FPGA的可编程逻辑块

    公开(公告)号：US07911227B2

    公开(公告)日：2011-03-22

    申请号：US12633731

    申请日：2009-12-08

    Applicant: Byoung Gon Yu ,  Yong-Joo Kim ,  Sung Min Yoon ,  Seung-Yun Lee ,  Young Sam Park ,  Soonwon Jung

    Inventor： Byoung Gon Yu ,  Yong-Joo Kim ,  Sung Min Yoon ,  Seung-Yun Lee ,  Young Sam Park ,  Soonwon Jung

    IPC: G06F7/38 ,  H03K19/173

    CPC classification number: H03K19/17784 ,  H03K19/17728 ,  H03K19/17792

    Abstract: Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.

    Abstract translation: 提供了现场可编程门阵列（FPGA）的可编程逻辑块。 可编程逻辑块包括连接到电源的上拉访问晶体管，连接到上拉存取晶体管的上变相存储器件，连接到上变相存储晶体管的下变相存储器件 存储器件，上变相存储器件和下变相存储器件之间的输出端子以及连接到下变相存储器件和地的下拉存取晶体管。 上变相存储器件和下变相存储器件的电阻值被单独编程。

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