公开(公告)号：US09153531B1

公开(公告)日：2015-10-06

申请号：US14192731

申请日：2014-02-27

Applicant: Altera Corporation

Inventor： Aron Joseph Roth ,  Michael Chan ,  Jeffrey Christopher Chromczak

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  G06F17/5077 ,  G06F2217/82 ,  H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may be associated with a given tile type, and each tile type may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a given tile, which is sometimes also referred to as wire twisting. Wire twists may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires. At the same time, the twist region height (i.e., the region in the tile in which wires are twisted) may be reduced compared to conventional interconnect circuitry.

Abstract translation: 集成电路可以具有可以包括瓦片序列的互连电路。 每个瓦片可以与给定的瓦片类型相关联，并且每个瓦片类型可以包括在多个轨道上的多条线路的预定布线。 导线可能会改变给定瓦片内的轨迹，有时也称为线扭。 电线扭曲可以减少相邻导线对之间的重叠，从而减小相应导线之间的耦合电容。 降低耦合电容可能导致导线之间的串扰减少，这可能加速沿着这些导线的信号转换。 同时，与传统的互连电路相比，扭转区域高度（即，电线被扭曲的瓦片中的区域）可以减少。

公开(公告)号：US10191661B1

公开(公告)日：2019-01-29

申请号：US15228989

申请日：2016-08-04

Applicant: ALTERA CORPORATION

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Jeffrey Christopher Chromczak ,  Herman Henry Schmit

IPC: G11C11/419 ,  G06F3/06 ,  G06F11/10

Abstract: An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further includes a switch coupled to the first memory cell and controlled by the second memory cell, wherein the switch provides a defined value to be read in place of the stored data of the first memory cell when the second memory cell stores the value indicating that the first memory cell is operating in the second mode.

公开(公告)号：US09564394B1

公开(公告)日：2017-02-07

申请号：US14546320

申请日：2014-11-18

Applicant: Altera Corporation

Inventor： Aron Joseph Roth ,  Jeffrey Christopher Chromczak ,  Michael Chan

IPC: G06F17/50 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/768 ,  G06F17/5077 ,  H01L23/522

Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.

Abstract translation: 集成电路可以具有可以包括瓦片序列的互连电路。 每个瓦片可以包括在多个轨道上的多条线路的预定路由。 电线可以通过线扭转或通过另一金属层中的通孔连接和电线来改变瓦片内的轨迹。 改变轨迹的电线可以减少相邻电线对之间的重叠，从而减小各个电线之间的耦合电容。 降低耦合电容可能导致导线之间的串扰减少，这可能加速沿着传统互连电路中的信号转换沿着这些导线的信号转变。 同时，将在下一个路由瓦片中结束的导线连接到在路由瓦片中开始的导线的路由瓦片中的次优线缝合可以实现有益的串扰，这可以进一步 提高信号转换时间。

公开(公告)号：US09824024B1

公开(公告)日：2017-11-21

申请号：US14530576

申请日：2014-10-31

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Jeffrey Christopher Chromczak ,  David Lewis

IPC: G06F12/00 ,  G06F12/1072 ,  G06F12/1009 ,  G06F13/28 ,  G06F12/0875

CPC classification number: G06F13/287 ,  H03K19/1776

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.

公开(公告)号：US09576625B1

公开(公告)日：2017-02-21

申请号：US14878958

申请日：2015-10-08

Applicant: Altera Corporation

Inventor： Jeffrey Christopher Chromczak

IPC: G11C7/12 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/12 ,  H03K19/17736 ,  H03K19/17748

Abstract: A method includes clearing configuration bits of a plurality of latches of an integrated circuit. The method also includes implementing an initialization routing pattern of the plurality of latches by configuring the configuration bits of the plurality of latches. The method further includes storing initialization data in a set of the plurality of latches based on the initialization routing pattern. The method includes clearing the configurations bit of the plurality of latches, wherein the initialization data remains stored in the set of the plurality of latches. The method also includes implementing a user-designed routing pattern of the plurality of latches by configuring the configuration bits of the plurality of latches.

Abstract translation: 一种方法包括清除集成电路的多个锁存器的配置位。 该方法还包括通过配置多个锁存器的配置位来实现多个锁存器的初始化路由模式。 该方法还包括基于初始化路由模式将初始化数据存储在多个锁存器的集合中。 该方法包括清除多个锁存器的配置位，其中初始化数据保持存储在多个锁存器的集合中。 该方法还包括通过配置多个锁存器的配置位来实现多个锁存器的用户设计的路由模式。

公开(公告)号：US09166570B2

公开(公告)日：2015-10-20

申请号：US13964901

申请日：2013-08-12

Applicant: Altera Corporation

Inventor： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC: H03K19/00 ,  H03K3/356 ,  H03K3/037 ,  H03K19/003 ,  H03K19/177

CPC classification number: H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract translation: 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：US20150134870A1

公开(公告)日：2015-05-14

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。

公开(公告)号：US10289585B1

公开(公告)日：2019-05-14

申请号：US14464237

申请日：2014-08-20

Applicant: Altera Corporation

Inventor： Jeffrey Christopher Chromczak

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in storage nodes of a pipeline element and the identical routing signal bypassing the pipeline element. A programming element may access the storage nodes of the pipeline elements for write operations and, if desired, for read operations. For example, the programming element may perform write operations to initialize the storage nodes to a known state during power-up operations or to reset the pipeline element. In addition, the programming element may perform reed operations for debug and testing purposes.

公开(公告)号：US20160239043A1

公开(公告)日：2016-08-18

申请号：US15141201

申请日：2016-04-28

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

公开(公告)号：US20140210510A1

公开(公告)日：2014-07-31

申请号：US13754579

申请日：2013-01-30

Applicant: Altera Corporation

Inventor： Jeffrey Christopher Chromczak

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/0175 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3296 ,  H03K19/00 ,  H03K19/17792 ,  Y02D10/126 ,  Y02D10/172

Abstract: Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.

Abstract translation: 提供具有顺序逻辑电路的集成电路。 顺序逻辑电路可以包括耦合在速度关键输入端和速度关键输出端之间的可连接时钟存储元件链。 组合逻辑电路可以插入在链中的每个相邻的可旁路计时存储元件对之间。 动态电压 - 频率缩放（DVFS）控制电路可以向组合逻辑电路提供可调节的电源电压，并且可以提供可调节的时钟信号以控制时钟存储元件。 DVFS控制电路可以用于选择性地启用至少一些可旁路时钟存储元件，同时禁用其他可旁路的时钟存储元件，使得可以在保持相同的工作频率的同时降低电源电压。 可以调整电源电压和时钟信号的频率以提供所需的电压 - 频率折衷。