公开(公告)号：US09153531B1

公开(公告)日：2015-10-06

申请号：US14192731

申请日：2014-02-27

Applicant: Altera Corporation

Inventor： Aron Joseph Roth ,  Michael Chan ,  Jeffrey Christopher Chromczak

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  G06F17/5077 ,  G06F2217/82 ,  H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may be associated with a given tile type, and each tile type may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a given tile, which is sometimes also referred to as wire twisting. Wire twists may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires. At the same time, the twist region height (i.e., the region in the tile in which wires are twisted) may be reduced compared to conventional interconnect circuitry.

Abstract translation: 集成电路可以具有可以包括瓦片序列的互连电路。 每个瓦片可以与给定的瓦片类型相关联，并且每个瓦片类型可以包括在多个轨道上的多条线路的预定布线。 导线可能会改变给定瓦片内的轨迹，有时也称为线扭。 电线扭曲可以减少相邻导线对之间的重叠，从而减小相应导线之间的耦合电容。 降低耦合电容可能导致导线之间的串扰减少，这可能加速沿着这些导线的信号转换。 同时，与传统的互连电路相比，扭转区域高度（即，电线被扭曲的瓦片中的区域）可以减少。

公开(公告)号：US09564394B1

公开(公告)日：2017-02-07

申请号：US14546320

申请日：2014-11-18

Applicant: Altera Corporation

Inventor： Aron Joseph Roth ,  Jeffrey Christopher Chromczak ,  Michael Chan

IPC: G06F17/50 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/768 ,  G06F17/5077 ,  H01L23/522

Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.

Abstract translation: 集成电路可以具有可以包括瓦片序列的互连电路。 每个瓦片可以包括在多个轨道上的多条线路的预定路由。 电线可以通过线扭转或通过另一金属层中的通孔连接和电线来改变瓦片内的轨迹。 改变轨迹的电线可以减少相邻电线对之间的重叠，从而减小各个电线之间的耦合电容。 降低耦合电容可能导致导线之间的串扰减少，这可能加速沿着传统互连电路中的信号转换沿着这些导线的信号转变。 同时，将在下一个路由瓦片中结束的导线连接到在路由瓦片中开始的导线的路由瓦片中的次优线缝合可以实现有益的串扰，这可以进一步 提高信号转换时间。