公开(公告)号：US09922157B1

公开(公告)日：2018-03-20

申请号：US14802702

申请日：2015-07-17

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Herman Henry Schmit ,  Dana How ,  Mahesh A. Iyer ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

公开(公告)号：US09813061B1

公开(公告)日：2017-11-07

申请号：US15150869

申请日：2016-05-10

Applicant: Altera Corporation

Inventor： Herman Henry Schmit ,  David Lewis

IPC: H03K19/003 ,  G06F7/501 ,  H03K19/23 ,  H03K19/007 ,  G06F11/20

CPC classification number: H03K19/00392 ,  G06F7/501 ,  G06F11/187 ,  G06F11/2089 ,  G06F11/2094 ,  H03K19/00369 ,  H03K19/0075 ,  H03K19/23

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

公开(公告)号：US20170041249A1

公开(公告)日：2017-02-09

申请号：US15298122

申请日：2016-10-19

Applicant: Altera Corporation

Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

IPC: H04L12/933 ,  H04L12/927 ,  H04L12/24

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

公开(公告)号：US09553762B1

公开(公告)日：2017-01-24

申请号：US14316433

申请日：2014-06-26

Applicant: Altera Corporation

Inventor： Dana How ,  Herman Henry Schmit ,  Sean R. Atsatt

IPC: H04L12/50 ,  H04L12/24

CPC classification number: H04L45/06

Abstract: Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

Abstract translation: 本文提供的系统和方法用于提供包括可配置的节点阵列的NoC，其中节点的可配置阵列的节点以默认操作模式运行，直到触发替换操作模式。 例如，当NoC未被配置时，可以将锁存库初始化为“清除”，使得不存储路由决定。 这可以启用默认操作模式，其中路由逻辑根据需要更新锁存器的值，以便以动态方式实现所需的路由行为，直到执行配置。

公开(公告)号：US09300421B2

公开(公告)日：2016-03-29

申请号：US14058718

申请日：2013-10-21

Applicant: Altera Corporation

Inventor： Haiyun Yang ,  David W. Mendel ,  Keith Duwel ,  Huy Ngo ,  Herman Henry Schmit

IPC: H04J3/06

CPC classification number: H04J3/0697 ,  H04J3/0667 ,  H04L1/0042

Abstract: Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

Abstract translation: 公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统 正在由通信系统使用。 通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。 从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

公开(公告)号：US10523207B2

公开(公告)日：2019-12-31

申请号：US14460548

申请日：2014-08-15

Applicant: Altera Corporation

Inventor： Dana How ,  Sean R. Atsatt ,  Michael David Hutton ,  Herman Henry Schmit

IPC: H03K19/177 ,  H03K19/007

Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

公开(公告)号：US10044344B2

公开(公告)日：2018-08-07

申请号：US15798172

申请日：2017-10-30

Applicant: ALTERA CORPORATION

Inventor： Dana How ,  Herman Henry Schmit

IPC: H03K3/00 ,  H03K3/037

Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.

公开(公告)号：US20180069533A1

公开(公告)日：2018-03-08

申请号：US15798172

申请日：2017-10-30

Applicant: ALTERA CORPORATION

Inventor： Dana How ,  Herman Henry Schmit

IPC: H03K3/037

CPC classification number: H03K3/037 ,  H03K19/17744

Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.

公开(公告)号：US20170316120A1

公开(公告)日：2017-11-02

申请号：US15650318

申请日：2017-07-14

Applicant: Altera Corporation

Inventor： Michael David Hutton ,  Herman Henry Schmit

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

公开(公告)号：US09606573B1

公开(公告)日：2017-03-28

申请号：US14752393

申请日：2015-06-26

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Dana How ,  Herman Henry Schmit ,  Vadim Gutnik ,  Ramanand Venkata

IPC: H03K3/00 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.