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    Programmable circuit having multiple sectors
    1.
    发明授权
    Programmable circuit having multiple sectors 有权

    公开(公告)号：US10523207B2

    公开(公告)日：2019-12-31

    申请号：US14460548

    申请日：2014-08-15

    Applicant: Altera Corporation

    Inventor： Dana How ,  Sean R. Atsatt ,  Michael David Hutton ,  Herman Henry Schmit

    IPC: H03K19/177 ,  H03K19/007

    Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

    METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STORAGE CIRCUITS
    3.
    发明申请
    METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STORAGE CIRCUITS 审中-公开
    用于嵌入存储电路中的错误校正码的方法和装置

    公开(公告)号：US20160378599A1

    公开(公告)日：2016-12-29

    申请号：US15251951

    申请日：2016-08-30

    Applicant: Altera Corporation

    Inventor： Herman Henry Schmit ,  Michael David Hutton

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/0787 ,  G06F11/1004 ,  G06F11/1012 ,  G06F11/1044 ,  G06F17/5054 ,  G11C29/52 ,  H03M13/05

    Abstract: A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.

    Abstract translation: 计算机辅助设计（CAD）工具可以识别配置数据中的无关位。 不关心配置数据中的位可能会改变极性，而不影响电路设计的功能。 CAD工具可以计算错误校验码（例如，用于二维奇偶校验的奇偶校验位），并将错误校验码插入到配置数据中。 作为示例，CAD工具可以用错误代码替代配置数据中的无关位。 配置数据可以存储在可编程集成电路上的配置存储器单元中，从而在可编程集成电路上实现具有错误代码的电路设计。 在执行期间，可编程集成电路可以基于嵌入的错误代码执行错误检查并检测和纠正配置数据中的错误。

    Programmable Logic Device With Integrated Network-On-Chip
    4.
    发明申请
    Programmable Logic Device With Integrated Network-On-Chip 审中-公开
    集成片上系统的可编程逻辑器件

    公开(公告)号：US20170041249A1

    公开(公告)日：2017-02-09

    申请号：US15298122

    申请日：2016-10-19

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

    IPC: H04L12/933 ,  H04L12/927 ,  H04L12/24

    CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

    Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

    Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

    Programmable interposer circuitry
    5.
    发明授权
    Programmable interposer circuitry 有权
    可编程内插器电路

    公开(公告)号：US09106229B1

    公开(公告)日：2015-08-11

    申请号：US13829965

    申请日：2013-03-14

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Richard Arthur Grenier

    IPC: H03K19/173 ,  G06F17/50

    CPC classification number: H03K19/173 ,  G06F17/5077 ,  H01L22/22 ,  H01L23/147 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/014

    Abstract: A multichip package that includes a programmable interposer is provided. Multiple integrated circuits may be mounted on the interposer. Active circuitry may also be embedded in the interposer device to facilitate protocol-based communications, debugging, and other desired circuit operations. The interposer device may include programmable interconnect routing circuitry that serves primarily to provide routing for the different circuits within the multichip package. A design tool may be used to design the interposer device. The design tool may include a standard die footprint library from which standard interface templates can be selected when designing an interposer device that has to communicate various on-interposer integrated circuits. The use of standard die footprints may simplify the design of interposers by enabling a family of devices to interface with a given interposer.

    Abstract translation: 提供了一个包含可编程插入器的多芯片封装。 多个集成电路可以安装在插入器上。 有源电路也可以嵌入在插入器装置中以促进基于协议的通信，调试和其它期望的电路操作。 插入器设备可以包括可编程互连路由电路，其主要用于为多芯片封装内的不同电路提供路由。 可以使用设计工具来设计插入器设备。 该设计工具可以包括标准的裸片封装库，当设计必须通信各种内置插件集成电路的插入器装置时，可以从中标准接口模板被选择。 使用标准管芯封装可以通过使一系列器件与给定的插入器接口来简化插入器的设计。

    Integrated circuits with error handling capabilities
    7.
    发明授权
    Integrated circuits with error handling capabilities 有权
    具有错误处理能力的集成电路

    公开(公告)号：US09575862B1

    公开(公告)日：2017-02-21

    申请号：US14333408

    申请日：2014-07-16

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Dalon L. Westergreen

    IPC: H04L1/00 ,  G06F11/30 ,  G06F11/07

    CPC classification number: G06F11/076 ,  G01R31/00 ,  G06F11/0706 ,  G06F11/079 ,  G06F11/1004 ,  G06F11/1405 ,  G06F11/1666 ,  G06F11/186 ,  G06F17/5045 ,  G06F17/5054

    Abstract: A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.

    Abstract translation: 逻辑设计可以包括控制和数据路径电路。 数据路径电路可以以产生相应的第一和第二数据信号的双重模块冗余布置来实现。 控制电路可以以三重模块冗余布置来实现。 存储电路可用于缓冲第一和第二数据信号。 实时错误检测电路可以对第一和第二数据信号执行实时错误检测操作。 后台错误检查电路可以执行后台错误检查操作，例如对配置数据的循环冗余校验计算。 响应于由实时错误检测电路检测到的错误，电路可以在缓冲的第一和第二数据信号之间进行选择以产生输出数据信号。 可以基于背景错误检查操作来执行选择，并且可以相对于错误的实时检测来延迟该选择。

    Programmable logic device with integrated network-on-chip
    8.
    发明授权
    Programmable logic device with integrated network-on-chip 有权
    具有集成片上芯片的可编程逻辑器件

    公开(公告)号：US09479456B2

    公开(公告)日：2016-10-25

    申请号：US14066425

    申请日：2013-10-29

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

    IPC: H04L12/933 ,  G06F15/78

    CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

    Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

    Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

    PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
    9.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP 有权
    具有集成网络芯片的可编程逻辑器件

    公开(公告)号：US20140126572A1

    公开(公告)日：2014-05-08

    申请号：US14066425

    申请日：2013-10-29

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

    IPC: H04L12/931

    CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

    Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

    Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

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