公开(公告)号：US20240194752A1

公开(公告)日：2024-06-13

申请号：US18502352

申请日：2023-11-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Woo Kyung YOU ,  Sang Koo KANG ,  Jun Chae LEE ,  Koung Min RYU ,  Woo Jin LEE

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851

摘要： A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first direction, gate electrodes covering the active pattern and extending in a second direction, a gate spacer disposed on a sidewall of each of the gate electrodes, a source/drain pattern disposed between adjacent ones of the gate electrodes, an etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern, an interlayer insulating film disposed between the adjacent ones of the gate electrodes with a contact trench exposing the source/drain pattern defined therein, a liner film disposed on an outer sidewall of the contact trench, and a source/drain contact disposed on the liner film and filling the contact trench, in which the source/drain contact is connected to the source/drain pattern. At least a portion of the liner film may be disposed in the source/drain pattern.

公开(公告)号：US12009434B2

公开(公告)日：2024-06-11

申请号：US18098769

申请日：2023-01-19

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/4763 ,  H01L21/477 ,  H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L21/02565 ,  H01L21/47635 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

摘要： As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

公开(公告)号：US12009433B2

公开(公告)日：2024-06-11

申请号：US16001837

申请日：2018-06-06

申请人： Intel Corporation

发明人： Van H. Le ,  Inanc Meric ,  Gilbert Dewey ,  Sean Ma ,  Abhishek A. Sharma ,  Miriam Reshotko ,  Shriram Shivaraman ,  Kent Millard ,  Matthew V. Metz ,  Wilhelm Melitz ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78678 ,  H01L21/28194 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/7869

摘要： Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

公开(公告)号：US20240186219A1

公开(公告)日：2024-06-06

申请号：US18075034

申请日：2022-12-05

申请人： International Business Machines Corporation

发明人： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/6656 ,  H01L29/78696

摘要： A semiconductor structure includes a first backside power rail disposed on a portion of a sidewall and a bottom surface of a backside source/drain contact, a first sidewall spacer disposed on another sidewall of the backside source/drain contact, and a backside signal line disposed on the first sidewall spacer and separated from the backside source/drain contact.

公开(公告)号：US20240186180A1

公开(公告)日：2024-06-06

申请号：US18438653

申请日：2024-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Lun Chang ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC分类号： H01L21/768 ,  H01L21/306 ,  H01L21/762 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/7682 ,  H01L21/7624 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696

摘要： An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

公开(公告)号：US12002877B2

公开(公告)日：2024-06-04

申请号：US17358500

申请日：2021-06-25

申请人： The Research Foundation for the State University of New York

发明人： Huamin Li ,  Fei Yao

IPC分类号： H01L29/775 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/775 ,  H01L29/41733 ,  H01L29/42384

摘要： Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.

公开(公告)号：US20240178324A1

公开(公告)日：2024-05-30

申请号：US18518735

申请日：2023-11-24

申请人： Samsung Electronics Co., Ltd. ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

发明人： Kwanghee LEE ,  Jinseong PARK ,  Sangwook KIM ,  Hyemi KIM ,  Seonghwan RYU

IPC分类号： H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/6675 ,  H01L29/78696

摘要： Provided are a crystalline InZnO oxide semiconductor, a method of forming the same, and a semiconductor device including the crystalline InZnO oxide semiconductor. The crystalline InZnO oxide semiconductor includes an oxide including In and Zn, wherein in Inductively Coupled Plasma-Mass Spectrometry (ICP-MS) analysis, a content of In among In and Zn is about 30 at % or more and about 75 at % or less, and the crystalline InZnO oxide semiconductor has a peak showing crystallinity at a 2-theta value between about 32.3 degrees and about 33.3 degrees in X-ray diffraction (XRD) analysis.

公开(公告)号：US20240178302A1

公开(公告)日：2024-05-30

申请号：US18097274

申请日：2023-01-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Ren CHEN ,  Chung-Ting LI

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66515 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

公开(公告)号：US20240178142A1

公开(公告)日：2024-05-30

申请号：US18060056

申请日：2022-11-30

申请人： International Business Machines Corporation

发明人： Shravana Kumar Katakam ,  Tao Li ,  Indira Seshadri ,  Ruilong Xie

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/823871 ,  H01L23/5283 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The first nanodevice includes a first source/drain contact. The second nanodevice includes a second source/drain contact. The second nanodevice is located adjacent to and parallel to the first nanodevice. A power bar is located between the first nanodevice and the second nanodevice. The power bar is connected to the second source/drain contact. A top surface of the power bar and the second source/drain contact are substantially in a same plane. The top surface of the power bar and the second source/drain contact are substantially a same height.

公开(公告)号：US20240178128A1

公开(公告)日：2024-05-30

申请号：US18099952

申请日：2023-01-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hong-Chih CHEN ,  Chun-Sheng LIANG ,  Yu-San CHIEN ,  Wei-Chih KAO

IPC分类号： H01L23/522 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5226 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66545 ,  H01L29/78696

摘要： A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.