公开(公告)号：US3733590A

公开(公告)日：1973-05-15

申请号：US3733590D

申请日：1971-04-15

Applicant: KAUFMAN A

Inventor： KAUFMAN A

IPC: G11C8/00 ,  G11C11/22 ,  G11C11/56 ,  H04R17/08 ,  H04R17/00

CPC classification number: G11C8/005 ,  G11C11/22 ,  G11C11/5657 ,  H04R17/08

Abstract: Ceramic memories utilize an electrostrictive ceramic motor element mechanically bonded to a ferroelectric ceramic memory element. Signal or ''''bit'''' electrodes are disposed over only the portion of the memory element to which maximum stress is transmitted by the motor element. In disc shaped embodiments, the bit electrodes are restricted to the central 50 percent of the memory device surface; in rectangular embodiments, the bit electrodes are disposed along the longitudinal centerline of the memory element and have a width less than one-half that of the memory device. In other embodiments, a portion of the memory element ceramic slab performs a motor function, or alternatively, dual motor elements are employed. To prevent ringing, each memory device may employ a damping electrode fabricated of an electrically conductive alloy exhibiting mechanical damping capacity. Alternatively, the device may be mounted to a substrate by means of an energy absorbing material, or may have an edge mechanically clamped or adhesively bonded to the substrate to prevent ringing.

Abstract translation: 陶瓷存储器利用机械地结合到铁电陶瓷存储元件的电致伸缩陶瓷电动机元件。 信号或“位”电极仅设置在存储元件的由电动机元件传递最大应力的部分上。 在盘形实施例中，位电极限于存储器件表面的中心50％; 在矩形实施例中，位电极沿着存储元件的纵向中心线布置，并且具有小于存储器件的一半的宽度。 在其他实施例中，存储元件陶瓷板的一部分执行电机功能，或者替代地，采用双电机元件。 为了防止振铃，每个存储器件可以使用由表现出机械阻尼能力的导电合金制成的阻尼电极。 或者，该装置可以通过能量吸收材料安装到基板上，或者可以将边缘机械地夹紧或粘合到基板上以防止振铃。

公开(公告)号：US3531182A

公开(公告)日：1970-09-29

申请号：US3531182D

申请日：1968-09-11

Applicant: ATOMIC ENERGY COMMISSION

Inventor： LAND CECIL E ,  SCHUELER DONALD G

IPC: G02F1/055 ,  G11C11/22 ,  G11C11/56 ,  H01L41/187 ,  G02F3/00

CPC classification number: G11C11/5657 ,  G02F1/055 ,  G11C11/22 ,  G11C13/04

公开(公告)号：US20240203472A1

公开(公告)日：2024-06-20

申请号：US18589540

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fa-Shen Jiang ,  Hsia-Wei Chen ,  Hsun-Chung Kuang ,  Hai-Dang Trinh ,  Cheng-Yuan Tsai

IPC: G11C11/16 ,  G11C11/56 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00

CPC classification number: G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/5614 ,  G11C11/5657 ,  G11C11/5678 ,  H10B53/30 ,  H10B61/22 ,  H10B63/30

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

公开(公告)号：US20240121967A1

公开(公告)日：2024-04-11

申请号：US18376762

申请日：2023-10-04

Applicant: Terra Quantum AG

Inventor： Anna Razumnaja ,  Yurii Tikhonov ,  Igor Lukyanchuk ,  Valerii Vinokour

IPC: H10B53/30 ,  G06N3/045 ,  G11C11/22 ,  G11C11/54 ,  G11C11/56

CPC classification number: H10B53/30 ,  G06N3/045 ,  G11C11/221 ,  G11C11/54 ,  G11C11/5657

Abstract: A ferroelectric nanoparticle capacitor-device comprises a pair of conductive elements electrically insulated from each other, and ferroelectric nanoparticles arranged between the conductive elements of the pair. The ferroelectric nanoparticles are adapted to provide at least three polarization states with different total ferroelectric polarizations.

公开(公告)号：US20230282235A1

公开(公告)日：2023-09-07

申请号：US18316641

申请日：2023-05-12

Applicant: Resonac Corporation

Inventor： Masaaki YANAGISAWA

IPC: G11B9/02 ,  G11C11/22 ,  G11C11/56

CPC classification number: G11B9/02 ,  G11C11/22 ,  G11C11/221 ,  G11C11/5657 ,  G11B5/21

Abstract: A ferroelectric recording medium includes an electrode layer, a ferroelectric recording layer, and a protection layer formed in this order on a substrate, wherein the ferroelectric recording layer includes a ferroelectric layer, the ferroelectric layer has an amorphous structure with short-range order, a distance of the short-range order is equal to or less than 2 nm, and a lattice constant of the amorphous structure and the lattice constant of the material constituting the substrate are lattice-matched within a range of ±10%.

公开(公告)号：US11735244B2

公开(公告)日：2023-08-22

申请号：US17562557

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/00 ,  G11C11/56

CPC classification number: G11C11/2273 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293 ,  G11C11/5657 ,  G11C11/22

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US11723214B2

公开(公告)日：2023-08-08

申请号：US17729750

申请日：2022-04-26

Applicant: SK hynix Inc.

Inventor： Hwang Yeon Kim

IPC: G11C11/00 ,  H10B53/50 ,  G11C11/22 ,  H10B53/30 ,  G11C11/56 ,  H10B51/00

CPC classification number: H10B53/50 ,  G11C11/22 ,  G11C11/56 ,  H10B53/30 ,  G11C11/5657 ,  H10B51/00

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

公开(公告)号：US11688435B2

公开(公告)日：2023-06-27

申请号：US17882478

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Wolfgang Anton Spirkl ,  Michael Dieter Richter ,  Martin Brox ,  Thomas Hein

IPC: G06G7/12 ,  G11C5/14 ,  G11C11/56 ,  G11C7/10 ,  G11C11/22

CPC classification number: G11C5/147 ,  G11C5/148 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/56 ,  G11C11/5657

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

公开(公告)号：US20190156887A1

公开(公告)日：2019-05-23

申请号：US15821240

申请日：2017-11-22

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Jeremy M. Hirst

IPC: G11C13/00

CPC classification number: G11C13/0061 ,  G11C11/00 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/5657 ,  G11C13/004 ,  G11C2013/0054

Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.

公开(公告)号：US20180358075A1

公开(公告)日：2018-12-13

申请号：US16032398

申请日：2018-07-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/005 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293 ,  G11C11/5657

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.