Controlled heating of a memory device

    公开(公告)号:US12210774B2

    公开(公告)日:2025-01-28

    申请号:US17677568

    申请日:2022-02-22

    Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

    Data inversion techniques
    2.
    发明授权

    公开(公告)号:US11601215B2

    公开(公告)日:2023-03-07

    申请号:US17149196

    申请日:2021-01-14

    Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

    DYNAMIC CONTROL OF ERROR MANAGEMENT AND SIGNALING

    公开(公告)号:US20230030776A1

    公开(公告)日:2023-02-02

    申请号:US17963367

    申请日:2022-10-11

    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

    Drive strength calibration for multi-level signaling

    公开(公告)号:US11443779B2

    公开(公告)日:2022-09-13

    申请号:US17241876

    申请日:2021-04-27

    Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

    Pre-distortion for multi-level signaling

    公开(公告)号:US11349526B2

    公开(公告)日:2022-05-31

    申请号:US17078812

    申请日:2020-10-23

    Abstract: Methods, systems, and devices for pre-distortion of multi-level signaling are described. A device may identify two multi-level signals that are to be transmitted over two transmission lines at the same time. The device may estimate the crosstalk expected to be caused by one of the multi-level signals on the other during propagation. Based on the expected crosstalk, the device may generate a signal that compensates for the expected crosstalk. In some examples, the signal may be a combination of the first signal and a cancelation signal. In some examples, once the compensated signal has been generated, it is transmitted over its respective transmission line at the same time that the other multi-level is transmitted over its respective transmission line.

    Bit and signal level mapping
    7.
    发明授权

    公开(公告)号:US11327832B2

    公开(公告)日:2022-05-10

    申请号:US17150480

    申请日:2021-01-15

    Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

    TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK

    公开(公告)号:US20220100604A1

    公开(公告)日:2022-03-31

    申请号:US17493985

    申请日:2021-10-05

    Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

    DYNAMICALLY CONFIGURING TRANSMISSION LINES OF A BUS

    公开(公告)号:US20220027296A1

    公开(公告)日:2022-01-27

    申请号:US17393819

    申请日:2021-08-04

    Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.

    Dynamic control of error management and signaling

    公开(公告)号:US11138064B2

    公开(公告)日:2021-10-05

    申请号:US16711354

    申请日:2019-12-11

    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Error thresholds for a memory device are configurable based on parameters such as a type of data or a location of stored data. When retrieving the data, the memory device tracks or counts errors in the data and determines whether the error threshold has been satisfied. The memory device transmits (e.g., to a host device) an indication of whether the error threshold has been satisfied, and the system is configured to perform functions to correct the errors and/or prevent further errors. The memory device is also configured to identify errors in received commands or to identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

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