-
公开(公告)号：US20240040936A1
公开(公告)日：2024-02-01
申请号：US18447856
申请日：2023-08-10
Inventor： Ku-Feng Lin
CPC classification number: H10N50/80 , G11C11/1655 , G11C11/1657 , H10B61/22 , H10N50/01
Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
-
公开(公告)号：US11854617B2
公开(公告)日：2023-12-26
申请号：US18156707
申请日：2023-01-19
Inventor： Hiroki Noguchi , Ku-Feng Lin
CPC classification number: G11C13/004 , G11C13/0026 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
Abstract: A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.
-
公开(公告)号：US11631440B2
公开(公告)日：2023-04-18
申请号：US17731248
申请日：2022-04-27
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
-
公开(公告)号：US20220336037A1
公开(公告)日：2022-10-20
申请号：US17856756
申请日：2022-07-01
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
-
公开(公告)号：US09214931B2
公开(公告)日：2015-12-15
申请号：US13906513
申请日：2013-05-31
Inventor： Ku-Feng Lin , Hung-Chang Yu
CPC classification number: H03K5/2481 , G11C7/062 , G11C13/004 , G11C2013/0054
Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.
Abstract translation: 提供具有减小的偏置钳位的感测电路和操作感测电路的方法。 感测电路可以包括参考路径和感测路径。 感测路径可以包括第一晶体管，钳位电容器和一对开关。 参考路径可以包括第二晶体管，钳位电容器和另一对开关。 接收偏置电压的公共增益级在充电模式下为相应路径的钳位电容器充电。 夹紧电容器可以在充电模式期间以串联或部分平行的方式充电。 每个路径可以耦合到比较器，比较器可以在感测模式期间感测路径之间的电流或电压变化。 感测电路可以被配置为提供以并行或串行方式感测多个感测和/或参考路径之间的电流或电压变化。
-
Patent Agency Ranking
公开(公告)号：US09165613B2
公开(公告)日：2015-10-20
申请号：US14016917
申请日：2013-09-03
Inventor： Ku-Feng Lin , Hung-Chang Yu , Yue-Der Chih
CPC classification number: G11C7/062 , G11C7/067 , G11C7/08 , G11C27/02 , G11C2207/063
Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
Abstract translation: 器件包括放大器和第一开关电流采样器。 第一开关电流采样器包括第一晶体管，第一电容器以及第一，第二和第三开关。 第一电容器具有电连接到第一晶体管的栅电极的第一端子和与第一晶体管的源电极电连接的第二端子。 第一开关具有电连接到第一电流源的第一端子和电连接到第一晶体管的栅电极的第二端子。 第二开关具有电连接到第一电流源的第一端子和与第一晶体管的漏电极电连接的第二端子。 第三开关具有电连接到第一晶体管的漏电极的第一端子和与放大器的第一输入端子电连接的第二端子。
-
公开(公告)号：US20250157500A1
公开(公告)日：2025-05-15
申请号：US19021205
申请日：2025-01-15
Inventor： Ku-Feng Lin
IPC: G11C7/06
Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.
-
公开(公告)号：US20240386977A1
公开(公告)日：2024-11-21
申请号：US18787706
申请日：2024-07-29
Inventor： Ku-Feng Lin , Perng-Fei Yuh , Meng-Sheng Chang
IPC: G11C17/16
Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.
-
59.发明公开公开(公告)号：US20240296887A1
公开(公告)日：2024-09-05
申请号：US18662806
申请日：2024-05-13
Inventor： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC: G11C14/00 , G11C11/16 , G11C11/419
CPC classification number: G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
-
公开(公告)号：US11962332B2
公开(公告)日：2024-04-16
申请号：US18165025
申请日：2023-02-06
Inventor： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC classification number: H03M7/16 , G11C11/1673 , H03K19/20
Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
-
-
-
-
-
-
-
-
-
Search Results
73
records
(took 0.021 seconds)
