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51.发明授权公开(公告)号：US09666271B2
公开(公告)日：2017-05-30
申请号：US14218058
申请日：2014-03-18
发明人： Tatsuya Onuki
IPC分类号： G11C7/16 , G11C11/56 , G11C11/403 , G11C11/4076 , G11C11/4091
CPC分类号： G11C11/565 , G11C11/403 , G11C11/4076 , G11C11/4091
摘要： To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
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公开(公告)号：US09647665B2
公开(公告)日：2017-05-09
申请号：US14967553
申请日：2015-12-14
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/00
CPC分类号： H03K19/018521 , H03K3/356104 , H03K19/0016
摘要： To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.
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公开(公告)号：US09553204B2
公开(公告)日：2017-01-24
申请号：US14667794
申请日：2015-03-25
发明人： Takanori Matsuzaki , Tatsuya Onuki
IPC分类号： G11C11/404 , H01L29/786 , H01L27/12 , H01L27/115
CPC分类号： H01L29/7869 , G11C11/404 , H01L27/1156 , H01L27/1225 , H01L27/124
摘要： A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.
摘要翻译： 提供了一种写入操作优异的半导体器件。 在提供给源极线的数据电压通过位线被提供给存储单元的节点的结构中，在连接到位线的存储器单元之间提供开关。 在将数据电压提供给存储单元的节点的期间内，位于存储单元之间的位线上的开关断开。 通过这样的结构，能够减少向存储单元的节点提供数据电压的期间的位线的寄生电容。 结果，可以快速地执行将数据电压写入存储单元。
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公开(公告)号：US09349435B2
公开(公告)日：2016-05-24
申请号：US14679111
申请日：2015-04-06
发明人： Tatsuya Onuki
IPC分类号： G11C11/24 , G11C11/4091 , G11C11/4097 , H01L29/786 , H01L27/108 , G11C7/10 , G11C11/4094 , G11C29/04
摘要： Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.
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公开(公告)号：US09312269B2
公开(公告)日：2016-04-12
申请号：US14272853
申请日：2014-05-08
发明人： Kiyoshi Kato , Tatsuya Onuki
IPC分类号： H01L29/10 , H01L29/12 , H01L27/115 , H01L27/108 , G11C11/00 , H01L27/105 , G11C14/00 , H01L27/11
CPC分类号： H01L27/11563 , G11C11/005 , G11C11/412 , G11C14/0054 , H01L27/105 , H01L27/10805 , H01L27/10894 , H01L27/1104 , H01L27/1108 , H01L27/1156 , H01L27/1225
摘要： A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.
摘要翻译： 具有新型结构的半导体器件，其中提供了即使使用小型化元件来保持数据所需的存储容量。 在半导体器件中，电容器的电极是设置在与晶体管的栅极相同的层中的电极和设置在与晶体管的源极和漏极相同的层中的电极。 此外，在不同的层中设置提供晶体管的栅极的层和连接多个存储器中的晶体管的栅极的布线层。 利用这种结构，可以减小在晶体管的栅极周围形成的寄生电容，并且可以在更大的面积中形成电容器。
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公开(公告)号：US09299432B2
公开(公告)日：2016-03-29
申请号：US13889957
申请日：2013-05-08
发明人： Tatsuya Onuki , Wataru Uesugi
CPC分类号： G11C14/0054 , G11C5/063 , G11C5/10
摘要： To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.
摘要翻译： 提供一种包括实现高速操作和较低功耗的易失性存储器的半导体器件。 例如，半导体器件包括设置有第一和第二数据保持部分的SRAM和设置有第三和第四第二数据保持部分的非易失性存储器。 第一数据保持部分通过晶体管与第四数据保持部分电连接。 第二数据保持部分通过晶体管与第三数据保持部分电连接。 当SRAM保存数据时，晶体管导通，以便SRAM和非易失性存储器都保存数据。 然后，在供电停止之前晶体管截止，使得数据变得非易失性。
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公开(公告)号：US09245650B2
公开(公告)日：2016-01-26
申请号：US14199584
申请日：2014-03-06
发明人： Hiroki Inoue , Kei Takahashi , Tatsuya Onuki
CPC分类号： H03K5/2481 , G11C27/024 , G11C27/026 , H03K5/249
摘要： A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.
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公开(公告)号：US20130301331A1
公开(公告)日：2013-11-14
申请号：US13889957
申请日：2013-05-08
发明人： Tatsuya Onuki , Wataru Uesugi
CPC分类号： G11C14/0054 , G11C5/063 , G11C5/10
摘要： To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.
摘要翻译： 提供一种包括实现高速操作和较低功耗的易失性存储器的半导体器件。 例如，半导体器件包括设置有第一和第二数据保持部分的SRAM和设置有第三和第四第二数据保持部分的非易失性存储器。 第一数据保持部分通过晶体管与第四数据保持部分电连接。 第二数据保持部分通过晶体管与第三数据保持部分电连接。 当SRAM保存数据时，晶体管导通，以便SRAM和非易失性存储器都保存数据。 然后，在供电停止之前晶体管截止，使得数据变得非易失性。
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公开(公告)号：US12086954B2
公开(公告)日：2024-09-10
申请号：US17768726
申请日：2020-10-19
发明人： Yuki Okamoto , Tatsuya Onuki
IPC分类号： G06T3/40 , G02F1/1362 , G02F1/1368 , G06T1/20 , G06T3/4046 , G09G3/36 , G09G3/32
CPC分类号： G06T3/4046 , G02F1/136286 , G02F1/1368 , G06T1/20 , G09G3/3688 , G09G3/32 , G09G2300/023 , G09G2340/0407
摘要： A display apparatus that can display a high-resolution image can be provided. In the display apparatus, a first layer and a second layer are stacked. In the first layer, an arithmetic circuit and a data driver circuit and are provided, and in the second layer, a display portion is provided. In the arithmetic circuit, a neural network is configured. The display portion has a region overlapping with the data driver circuit. The arithmetic circuit has a function of performing arithmetic processing using the neural network on image data and supplying the arithmetically-processed image data to the data driver circuit.
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公开(公告)号：US12069846B2
公开(公告)日：2024-08-20
申请号：US17424621
申请日：2019-11-18
IPC分类号： H10B12/00 , H01L27/12 , H01L29/24 , H01L29/786
CPC分类号： H10B12/00 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/78648 , H01L29/78651 , H01L29/7869
摘要： A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.
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