公开(公告)号：US12063798B2

公开(公告)日：2024-08-13

申请号：US18203736

申请日：2023-05-31

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC分类号： H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC分类号： H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

摘要： A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US11876138B2

公开(公告)日：2024-01-16

申请号：US17284553

申请日：2019-10-15

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Eri Sato ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

IPC分类号： H03F3/45 ,  H01L29/786 ,  H01L29/24

CPC分类号： H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

摘要： A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

公开(公告)号：US11854599B2

公开(公告)日：2023-12-26

申请号：US17977099

申请日：2022-10-31

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takahiko Ishizu ,  Yuto Yakubo ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC分类号： G11C11/40 ,  G11C11/4074 ,  G11C11/4096 ,  H01L29/786 ,  H01L27/12 ,  H10B99/00

CPC分类号： G11C11/4074 ,  G11C11/4096 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H10B99/00

摘要： Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

公开(公告)号：US11696455B2

公开(公告)日：2023-07-04

申请号：US17509157

申请日：2021-10-25

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC分类号： H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC分类号： H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

摘要： A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US11657867B2

公开(公告)日：2023-05-23

申请号：US17377757

申请日：2021-07-16

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC分类号： G11C11/40 ,  G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H01L27/108

CPC分类号： G11C11/4091 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10805

摘要： A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

公开(公告)号：US11423975B2

公开(公告)日：2022-08-23

申请号：US16968922

申请日：2019-02-13

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yuki Okamoto ,  Tatsuya Onuki

IPC分类号： G11C11/4097 ,  G11C11/4091 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

公开(公告)号：US11366507B2

公开(公告)日：2022-06-21

申请号：US17104460

申请日：2020-11-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

IPC分类号： G11C14/00 ,  G06F1/3234 ,  G11C5/14 ,  G11C16/30

摘要： To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US11289475B2

公开(公告)日：2022-03-29

申请号：US16695385

申请日：2019-11-26

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei Yamazaki ,  Tatsuya Onuki ,  Katsuaki Tochibayashi

IPC分类号： H01L29/786 ,  H01L27/06 ,  H01L29/45

摘要： A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator. The capacitor includes a fifth conductor over the first insulator, the third insulator over the fifth conductor, and the second conductor over the third insulator.

公开(公告)号：US11270997B2

公开(公告)日：2022-03-08

申请号：US16757025

申请日：2018-11-19

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Tatsuya Onuki ,  Yuki Okamoto ,  Hisao Ikeda ,  Shuhei Nagatsuka

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

公开(公告)号：US11056491B2

公开(公告)日：2021-07-06

申请号：US16623648

申请日：2018-06-19

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC分类号： H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L29/24 ,  H01L29/66 ,  H01L21/477

摘要： A semiconductor device that can be highly integrated is provided. The semiconductor device includes a transistor, an interlayer film, and a first conductor. The transistor includes an oxide over a first insulator; a second conductor over the oxide; a second insulator provided between the oxide and the second conductor and in contact with a side surface of the second conductor; and a third insulator provided for the side surface of the second conductor with the second insulator therebetween. The oxide includes a first region, a second region, and a third region. The first region overlaps with the second conductor. The second region is provided between the first region and the third region. The third region has a lower resistance than the second region. The second region has a lower resistance than the first region. The interlayer film is provided over the first insulator and the oxide. The first conductor is electrically connected to the third region. The third region overlaps with one of the third insulator, the first conductor, and the interlayer film. A top surface of the third insulator is level with a top surface of the interlayer film.