公开(公告)号：US11899478B2

公开(公告)日：2024-02-13

申请号：US17298695

申请日：2019-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Keita Sato ,  Yuto Yakubo ,  Yoshiaki Oikawa ,  Shunpei Yamazaki

IPC: G05F1/56 ,  G05F1/595

CPC classification number: G05F1/56 ,  G05F1/595

Abstract: A low-power semiconductor device is provided. A retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of a source and a drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to a gate of the output transistor. A node to which the other of the source and the drain of the retention transistor and the gate of the output transistor are electrically connected is a retention node. When the retention transistor is in an on state, a potential corresponding to a potential output from the control circuit is written to the retention node. Then, when the retention transistor is in an off state, the potential of the retention node is retained. Thus, a gate potential of the output transistor can be kept at a constant value even when the control circuit is off. Accordingly, even when the control circuit is off, a constant potential can be continuously output from one of a source and a drain of the output transistor, for example.

公开(公告)号：US11876138B2

公开(公告)日：2024-01-16

申请号：US17284553

申请日：2019-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Eri Sato ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

IPC: H03F3/45 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

公开(公告)号：US11854599B2

公开(公告)日：2023-12-26

申请号：US17977099

申请日：2022-10-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko Ishizu ,  Yuto Yakubo ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C11/4074 ,  G11C11/4096 ,  H01L29/786 ,  H01L27/12 ,  H10B99/00

CPC classification number: G11C11/4074 ,  G11C11/4096 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H10B99/00

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

公开(公告)号：US20140319518A1

公开(公告)日：2014-10-30

申请号：US14328818

申请日：2014-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

Abstract translation: 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

公开(公告)号：US11869627B2

公开(公告)日：2024-01-09

申请号：US17606116

申请日：2020-05-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto Yakubo ,  Seiya Saito ,  Tatsuya Onuki

IPC: G11C11/34 ,  G11C7/12 ,  H10B12/00 ,  G11C11/401

CPC classification number: G11C7/12 ,  H10B12/20 ,  H10B12/312 ,  G11C11/401

Abstract: A semiconductor device is provided which includes a first control circuit including a first transistor in a silicon substrate channel, a second control circuit provided over the first control circuit, a memory circuit provided over the second control circuit, and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit.

公开(公告)号：US11823733B2

公开(公告)日：2023-11-21

申请号：US17600379

申请日：2020-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi Kunitake ,  Yuto Yakubo ,  Takanori Matsuzaki ,  Yuki Okamoto ,  Tatsuya Onuki

IPC: G11C5/06 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/789

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

公开(公告)号：US10446583B2

公开(公告)日：2019-10-15

申请号：US15911233

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/544 ,  H01L29/66

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US09911756B2

公开(公告)日：2018-03-06

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US09542977B2

公开(公告)日：2017-01-10

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka ,  Yuto Yakubo

IPC: G11C5/02 ,  H01L29/24 ,  H01L27/12 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US09525073B2

公开(公告)日：2016-12-20

申请号：US14723630

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Yoshiyuki Kobayashi ,  Yutaka Shionoiri ,  Yuto Yakubo ,  Shuhei Nagatsuka ,  Shunpei Yamazaki

IPC: G05F3/08 ,  G05F1/10 ,  G05F3/26 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L27/12 ,  H01L29/04 ,  H01L27/085 ,  H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/7869 ,  G05F3/262 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.

Abstract translation: 提供占据小面积的半导体器件。 半导体器件包括电阻器。 电阻器包括晶体管。 当漏极电压高于晶体管的栅极电压和阈值电压之间的差时，漏极电压的0.1V变化的晶体管的漏极电流的增加率优选地高于或等于1％。 半导体器件具有基于电阻器的电阻产生电压的功能。