公开(公告)号：US20210226009A1

公开(公告)日：2021-07-22

申请号：US16749897

申请日：2020-01-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/201 ,  H01L29/43 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

公开(公告)号：US20210118985A1

公开(公告)日：2021-04-22

申请号：US17022338

申请日：2020-09-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: Circuits employing on-diffusion (OD) edge (ODE) dummy gate structures in cell circuit with increased gate dielectric thickness to reduce leakage current are disclosed. A gate dielectric structure may be formed between a work function metal structure of an ODE dummy gate structure and an active semiconductor structure in a cell circuit, and is provided to be thicker than a gate dielectric structure formed between a work function metal structure and an active gate(s) in the cell circuit. Providing a gate dielectric structure of increased thickness can reduce damage to the gate dielectric structure providing isolation between the ODE dummy gate structure and the active semiconductor structure. Providing a gate dielectric structure of increased thickness can also reduce the gap area adjacent to the ends of the active semiconductor structures and thus reduce the volume of work function metal structure formed in the gaps to further reduce leakage current.

公开(公告)号：US10950609B2

公开(公告)日：2021-03-16

申请号：US16511153

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a static random-access memory (SRAM) implemented using both a gate-all-around (GAA)-type transistor and a fin field-effect transistor (FinFET). For example, certain aspects are directed to an SRAM memory cell having a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor, and a pass-gate (PG) transistor coupled between a bit line of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell. In certain aspects, at least one of the PU transistor, the PD transistor, or the PG transistor comprises a GAA transistor, and at least another one of the PU transistor, the PD transistor, or the PG transistor comprises a FinFET.

公开(公告)号：US20190385049A1

公开(公告)日：2019-12-19

申请号：US16012451

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Periannan Chidambaram

IPC: G06N3/063 ,  G06N3/08 ,  G11C11/54

Abstract: Methods, systems, and devices for an artificial neural network are described. In one example, an artificial neuron in an artificial neural network may include a resistor coupled with an input line and configured to indicate a synaptic weight and a fuse coupled with the resistor. The artificial neuron may also include a selection component coupled with the fuse and configured to activate the fuse for programming the resistor, and a second selection component coupled with the resistor and an output line, the second selection component configured to select the resistor for a read operation.

公开(公告)号：US10199462B2

公开(公告)日：2019-02-05

申请号：US15650042

申请日：2017-07-14

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

公开(公告)号：US20180158935A1

公开(公告)日：2018-06-07

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7391 ,  H01L27/0255 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/495 ,  H01L29/66356 ,  H01L29/7851

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

公开(公告)号：US09941377B2

公开(公告)日：2018-04-10

申请号：US15189325

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/32 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor devices with wider field gates for reduced gate resistance are disclosed. In one aspect, a semiconductor device is provided that employs a gate. The gate is a conductive line disposed above the semiconductor device to form transistors corresponding to active semiconductor regions. Each active semiconductor region has a corresponding channel region. Portions of the gate disposed over each channel region are active gates, and portions not disposed over the channel region, but that are disposed over field oxide regions, are field gates. A voltage differential between each active gate and a source of each corresponding transistor causes current flow in a channel region when the voltage differential exceeds a threshold voltage. The width of each field gate is a larger width than each active gate. The larger width of the field gates results in reduced gate resistance compared to devices with narrower field gates.

公开(公告)号：US20170074728A1

公开(公告)日：2017-03-16

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092

CPC classification number: G01K7/015 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

Abstract translation: 器件包括源极接触，漏极接触，栅极接触和身体接触。 身体接触件电耦合到温度感测电路。 源极触点，漏极接触，栅极接触和主体接触包括在鳍状场效应晶体管（finFET）中。

公开(公告)号：US20160372316A1

公开(公告)日：2016-12-22

申请号：US14746606

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L21/02 ,  H01L27/02 ,  G05B19/418 ,  H01L27/11

CPC classification number: H01L21/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/785

Abstract: In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

Abstract translation: 在特定方面，集成电路包括耦合到第一鳍式场效应晶体管（FinFET）器件的第一栅极结构。 集成电路包括耦合到第二FinFET器件的第二栅极结构。 第一栅极结构和第二栅极结构被电介质区域分开。 集成电路还包括具有与介电区域接触的第一表面，第一栅极结构和第二栅极结构的金属触点。

公开(公告)号：US12206001B2

公开(公告)日：2025-01-21

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.