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公开(公告)号:US09691747B1
公开(公告)日:2017-06-27
申请号:US14977068
申请日:2015-12-21
发明人: Bing Dang , John Knickerbocker
IPC分类号: H01L21/78 , H01L25/00 , H01L25/065 , H01L21/66 , H01L23/00 , H01L21/56 , H01L21/683 , H01L25/075 , H01L25/11 , H01L25/04 , H01L25/07
CPC分类号: H01L25/50 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L22/20 , H01L24/32 , H01L24/81 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/043 , H01L25/0652 , H01L25/0657 , H01L25/074 , H01L25/0756 , H01L25/117 , H01L25/167 , H01L25/18 , H01L2221/68322 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2223/6677 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73204 , H01L2224/80121 , H01L2224/80143 , H01L2224/81005 , H01L2224/95001 , H01L2224/95144 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要: Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.
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公开(公告)号:US20240334616A1
公开(公告)日:2024-10-03
申请号:US18194597
申请日:2023-03-31
CPC分类号: H05K3/4602 , H05K1/0212 , H05K1/0218 , H05K1/024 , H05K1/115 , H05K3/0017 , H05K3/0055 , H05K7/20509 , H05K2201/09145
摘要: A method for manufacturing an electronic package includes etching one or more lateral surfaces of a PCB laminate to expose power and ground planes of the PCB laminate. A protective coating is applied to the exposed power and ground planes. At least one heat-generating component is affixed to a top surface of the PCB laminate. A heat spreader having a base section and flanged edges is formed and attached to the heat-generating components and the PCB laminate lateral surfaces, where the flanged edges of the heat spreader are thermally connected to the PCB laminate lateral surfaces. During operation of the heat-generating components, the flanged edges dissipate heat from the PCB laminate lateral surfaces.
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公开(公告)号:US20240120705A1
公开(公告)日:2024-04-11
申请号:US17962434
申请日:2022-10-07
IPC分类号: H01S5/024 , H01L23/367 , H01L23/373
CPC分类号: H01S5/02469 , H01L23/367 , H01L23/373
摘要: A heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. In one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.
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公开(公告)号:US11908723B2
公开(公告)日:2024-02-20
申请号:US17541946
申请日:2021-12-03
发明人: Akihiro Horibe , Qianwen Chen , Risa Miyazawa , Michael P. Belyansky , John Knickerbocker , Takashi Hisada
IPC分类号: H01L21/68 , H01L21/683
CPC分类号: H01L21/681 , H01L21/6835 , H01L2221/6834 , H01L2221/68381
摘要: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.
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公开(公告)号:US11903734B2
公开(公告)日:2024-02-20
申请号:US16238143
申请日:2019-01-02
CPC分类号: A61B5/6826 , A61B5/6833 , G06F3/015 , H02S40/30
摘要: Systems, computer-implemented methods and/or computer program products that facilitate wearable multiplatform sensing are provided. In one embodiment, a computer-implemented method comprises: measuring, by a system operatively coupled to a processor, wirelessly on a nail plate, physiological data of an entity; integrating and synchronizing, by the system, the physiological data with other physiological data from one or more devices to form integrated physiological data; and analyzing, by the system, the integrated physiological data to detect one or more disorders.
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公开(公告)号:US11539088B2
公开(公告)日:2022-12-27
申请号:US16813071
申请日:2020-03-09
发明人: Bing Dang , Leanna Pancoast , Jae-Woong Nah , John Knickerbocker
IPC分类号: H01M50/10 , H01M10/052 , H01M10/04 , H01M50/116 , H01M50/543
摘要: Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.
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公开(公告)号:US11522243B2
公开(公告)日:2022-12-06
申请号:US17128371
申请日:2020-12-21
发明人: Qianwen Chen , Jae-Woong Nah , Bing Dang , Leanna Pancoast , John Knickerbocker
IPC分类号: H01M50/171 , H01M10/0585 , H01M50/191 , H01M50/197 , H01M50/186
摘要: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.
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公开(公告)号:US11315902B2
公开(公告)日:2022-04-26
申请号:US16788459
申请日:2020-02-12
发明人: John Knickerbocker
IPC分类号: H01L25/065 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/00 , H01L23/498 , H01L23/66 , H01L25/18
摘要: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface. The bridge is disposed on the substrate between the first semiconductor chip and the second semiconductor chip, and one or more of the smaller first chip connections is physically and electrically connected to a respective first bridge connection on the first part of the bridge surface and one or more of the smaller second chip connection is physically and electrically connected to a respective second bridge connection. Some embodiments, a large surface bridge with the bridge. The large surface bridge and bridge can have different configurations. The bridge thickness allows larger chip connections and smaller connections with high pitch to intermingled in a location within the module. Methods of manufacture are disclosed.
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公开(公告)号:US11101513B2
公开(公告)日:2021-08-24
申请号:US16121307
申请日:2018-09-04
发明人: Qianwen Chen , Bing Dang , Bo Wen , Marlon Agno , John Knickerbocker
IPC分类号: H01M50/116 , H01M10/0585 , H01M50/124 , H01M50/183
摘要: Techniques regarding a thin film battery, which can comprise one or more sealing layers, and a method of manufacturing thereof are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a thin film battery cell encapsulated in a multi-layer stack comprising an adhesive layer located between a first substrate layer and a second substrate layer. The apparatus can also comprise a metal sealing layer at least partially surrounding the multi-layer stack.
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公开(公告)号:US11049841B2
公开(公告)日:2021-06-29
申请号:US15688369
申请日:2017-08-28
IPC分类号: H01L23/498 , H01L23/552 , H01L23/60 , H01L23/00 , H01L25/065 , H01L23/367
摘要: A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.
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