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公开(公告)号：US20210145325A1
公开(公告)日：2021-05-20
申请号：US16689208
申请日：2019-11-20
摘要： Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.
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公开(公告)号：US20210137457A1
公开(公告)日：2021-05-13
申请号：US16677881
申请日：2019-11-08
发明人： Keiji Matsumoto , Bruno Michel
摘要： A method is presented for predicting heat stroke of a subject. The method includes an earbud covered with a waterproof moisture permeable membrane allowing for moisture penetration, the earbud including an infrared (IR) temperature sensor for measuring core body temperature of the subject, wherein the IR temperature sensor is covered with a waterproof IR transmittable film to inhibit water drops from contacting a detector of the IR temperature sensor, a first humidity sensor positioned within a sweat flow path within the earbud, a second humidity sensor positioned outside the earbud, and a sodium ion (Na+) concentration sensor for measuring hydration levels of the subject.
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公开(公告)号：US09558311B2
公开(公告)日：2017-01-31
申请号：US14525292
申请日：2014-10-28
发明人： Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F2217/78 , G06F2217/80 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sectional areas and corresponding lengths that satisfy the specified thermal resistance. The method can also include selecting, from a set of placement areas corresponding to the second set of wiring cross-sectional areas and corresponding lengths, a heat sink placement area that is greater than a lower size for a placement area and less than an upper size for a placement area.
摘要翻译： 公开了一种用于确定用于在芯片支撑衬底的表面上接收散热器的区域的面积的方法。 该方法可以包括响应于与衬底布线相关联的指定电压降，确定满足特定电压降的第一组布线横截面积和对应的长度。 该方法还可以包括通过响应于与衬底布线和绝缘层相关联的指定热阻从第一组中选择满足特定热阻的第二组布线横截面区域和对应的长度来确定。 该方法还可以包括从对应于第二组布线横截面区域和相应长度的一组放置区域中选择大于放置区域的较小尺寸并小于上部尺寸的散热器放置区域 用于放置区域。
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公开(公告)号：US20160217247A1
公开(公告)日：2016-07-28
申请号：US15086984
申请日：2016-03-31
发明人： Sayuri Hada , Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018 , G06F17/5068 , G06F17/5077 , G06F17/5086 , G06F2217/12 , Y02P90/265
摘要： A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, Δα, varies in a substrate. The method focuses in on the difference in Δα with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in Δα with a smaller length scale (high frequency) and corrects only the difference in Δα with a greater length scale. The distribution of the difference in Δα in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in Δα with a low frequency and the difference in Δα between before and after correction, thereby revealing a part that requires correction.
摘要翻译： 一种减少布线层的调整以减少多层基板的翘曲的方法，并且能够定位需要校正的布线层的一部分以减少翘曲。 平均热膨胀系数Δα的差在基板中变化。 该方法集中在与具有较小长度尺度（高频）的Δα的差异相比，具有与翘曲相对显着影响的较大长度尺度（低频）的Δα的差异，并且仅校正Δα的差异 更长的刻度。 确定基板平面中Δα差异的分布。 然后执行数字滤波以仅提取Δα与低频之间的差异以及校正之前和之后Δα的差异，从而显示需要校正的部分。
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5.发明授权公开(公告)号：US09330213B2
公开(公告)日：2016-05-03
申请号：US13850386
申请日：2013-03-26
发明人： Keiji Matsumoto
IPC分类号： H01L25/065 , G06F17/50 , H05K7/20 , H05K3/10
CPC分类号： G06F17/5036 , G06F17/5009 , G06F17/5068 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/15311 , H05K3/10 , H05K7/205 , Y10T29/49162
摘要： A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatuses include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
摘要翻译： 一种用于优化多层芯片中的供电和散热路线的计算机实现的结构。 该方法包括：通过密度设定多层芯片的导热热值，制备含有硅的基板，其中形成面对多层芯片的上表面侧的布线层，设置来自多层芯片的布线层的电力 使用硅的衬底，操纵电源的值，以及基于密度来操纵导热热值。 两种装置包括有机基板，多层芯片，含硅的基板，布线层和散热器，其中，所述部件被配置为执行上述方法的步骤。 配置装置的方法确保所有多层芯片都存储在有机基板的凹部中。
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6.发明申请公开(公告)号：US20130308278A1
公开(公告)日：2013-11-21
申请号：US13850386
申请日：2013-03-26
发明人： Keiji Matsumoto
CPC分类号： G06F17/5036 , G06F17/5009 , G06F17/5068 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/15311 , H05K3/10 , H05K7/205 , Y10T29/49162
摘要： A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatus's include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
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公开(公告)号：US20240334616A1
公开(公告)日：2024-10-03
申请号：US18194597
申请日：2023-03-31
CPC分类号： H05K3/4602 , H05K1/0212 , H05K1/0218 , H05K1/024 , H05K1/115 , H05K3/0017 , H05K3/0055 , H05K7/20509 , H05K2201/09145
摘要： A method for manufacturing an electronic package includes etching one or more lateral surfaces of a PCB laminate to expose power and ground planes of the PCB laminate. A protective coating is applied to the exposed power and ground planes. At least one heat-generating component is affixed to a top surface of the PCB laminate. A heat spreader having a base section and flanged edges is formed and attached to the heat-generating components and the PCB laminate lateral surfaces, where the flanged edges of the heat spreader are thermally connected to the PCB laminate lateral surfaces. During operation of the heat-generating components, the flanged edges dissipate heat from the PCB laminate lateral surfaces.
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公开(公告)号：US20240120705A1
公开(公告)日：2024-04-11
申请号：US17962434
申请日：2022-10-07
IPC分类号： H01S5/024 , H01L23/367 , H01L23/373
CPC分类号： H01S5/02469 , H01L23/367 , H01L23/373
摘要： A heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. In one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.
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公开(公告)号：US20240006371A1
公开(公告)日：2024-01-04
申请号：US17809574
申请日：2022-06-29
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L24/11 , H01L24/16 , H01L24/29 , H01L2224/11849 , H01L2224/1148 , H01L2224/16237 , H01L2224/2902 , H01L2224/0401 , H01L2224/73204 , H01L2224/81815
摘要： An interconnect system may connect a first semiconductor device with second semiconductor device. The interconnect system includes patterned mask, conductive pads, solder bumps, and an adhesion layer. The patterned mask may be retained after it is utilized to fabricate the conductive pads and the solder bumps. The patterned mask may be thinned, and the adhesion layer may be formed upon the thinned patterned mask and upon the solder bumps. The adhesion layer and the solder bumps may be partially removed or planarized and the top surface of the adhesion layer that remains between the solder bumps may be coplanar with the top surface of the solder bumps.
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公开(公告)号：US11647954B2
公开(公告)日：2023-05-16
申请号：US16677881
申请日：2019-11-08
发明人： Keiji Matsumoto , Bruno Michel
CPC分类号： A61B5/6817 , A61B5/0008 , A61B5/01 , A61B5/02433 , A61B5/0878 , A61B5/4266
摘要： A method is presented for predicting heat stroke of a subject. The method includes an earbud covered with a waterproof moisture permeable membrane allowing for moisture penetration, the earbud including an infrared (IR) temperature sensor for measuring core body temperature of the subject, wherein the IR temperature sensor is covered with a waterproof IR transmittable film to inhibit water drops from contacting a detector of the IR temperature sensor, a first humidity sensor positioned within a sweat flow path within the earbud, a second humidity sensor positioned outside the earbud, and a sodium ion (Na+) concentration sensor for measuring hydration levels of the subject.
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