CO-PACKAGE OPTICS ASSEMBLY
    1.
    发明公开

    公开(公告)号:US20240264392A1

    公开(公告)日:2024-08-08

    申请号:US18107299

    申请日:2023-02-08

    IPC分类号: G02B6/122

    CPC分类号: G02B6/4277

    摘要: Co-package optics structures are provided in which an electromagnetic radiation absorption material layer is used to attach an optical link and/or waveguide structure to a coupling area that is located on a photonic integrated chip. The electromagnetic radiation absorption material layer can provide permanent or a non-permanent attachment between the optical link and/or waveguide structure and the coupling area of the photonic integrated chip. In the non-permanent embodiment, testing can be performed to determine whether the optical link and/or waveguide structure is defective, and if determined to be defective, the defective optical link and/or waveguide structure can be replaced by a replacement optical link and/or waveguide structure by removing the electromagnetic radiation absorption material layer that attaches the defective structure.

    Multiple die assembly
    4.
    发明授权

    公开(公告)号:US11973058B2

    公开(公告)日:2024-04-30

    申请号:US17535664

    申请日:2021-11-25

    摘要: A semiconductor die package that has a substrate with one or more substrate layers with one or more substrate connections. A substrate layer can include one or more redistribution layers (RDLs). One or more dies (e.g., multiple dies) are disposed on a top substrate layer. The dies have one or more die external connections. Some of the die external connections are electrically connected to one or more substrate connections. One or more metallic dam stiffeners form into a dam enclosure that is disposed on and physically connected to the top substrate layer. The dam enclosure encloses one or more of the dies. The metallic dam enclosure has one or more electrically connected regions where the metallic dam enclosure is electrically connected to one or more of the substrate horizontal connections and one or more electrically insulated regions where the metallic dam enclosure is electrically insulated from one or more of the substrate horizontal connections and the substrate via connections. In different embodiments, the dam enclosure stiffens the substrates/package during manufacture, assembly, and operation; provides confinement for underfill application; and provides a heat conduction path for heat removal. Methods of manufacturing and assembling the die package are disclosed.

    CARRIER WAFER WITH MULTIPLE ANTIREFLECTIVE COATING LAYERS

    公开(公告)号:US20230087366A1

    公开(公告)日:2023-03-23

    申请号:US17447948

    申请日:2021-09-17

    摘要: A carrier wafer, a structure, and a method are disclosed. The carrier wafer includes a wafer layer having a first surface and a second surface opposite the first surface, a first antireflective coating (ARC) layer positioned on the first surface of the wafer layer, a second ARC layer positioned on a surface of the first ARC layer opposite the wafer layer, and a thin release layer positioned on a surface of the second ARC layer opposite the first ARC layer. The structure includes the carrier wafer and a semiconductor device substrate positioned over the thin release layer of the carrier wafer. The method includes obtaining a wafer layer, forming an ARC layer on a surface of the wafer layer, forming a second ARC layer on a surface of the first ARC layer opposite the wafer layer, and forming a thin release layer on the second ARC layer.

    High speed handling of ultra-small chips by selective laser bonding and debonding

    公开(公告)号:US11222862B2

    公开(公告)日:2022-01-11

    申请号:US16658675

    申请日:2019-10-21

    摘要: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

    PRECISION THIN ELECTRONICS HANDLING INTEGRATION

    公开(公告)号:US20210366789A1

    公开(公告)日:2021-11-25

    申请号:US16882624

    申请日:2020-05-25

    摘要: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.