公开(公告)号：US11908723B2

公开(公告)日：2024-02-20

申请号：US17541946

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Akihiro Horibe ,  Qianwen Chen ,  Risa Miyazawa ,  Michael P. Belyansky ,  John Knickerbocker ,  Takashi Hisada

IPC: H01L21/68 ,  H01L21/683

CPC classification number: H01L21/681 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

公开(公告)号：US11539080B2

公开(公告)日：2022-12-27

申请号：US16787167

申请日：2020-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker

IPC: H01M10/0585 ,  H01M10/052 ,  H01M10/04 ,  A61B5/00

Abstract: A method for integrating a thin film microbattery with electronic circuitry includes forming a release layer over a handler, forming a thin film microbattery over the release layer of the handler, removing the thin film microbattery from the handler, depositing the thin film microbattery on an interposer, forming electronic circuitry on the interposer, and sealing the thin film microbattery and the electronic circuitry to create individual microbattery modules.

公开(公告)号：US11522243B2

公开(公告)日：2022-12-06

申请号：US17128371

申请日：2020-12-21

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Jae-Woong Nah ,  Bing Dang ,  Leanna Pancoast ,  John Knickerbocker

IPC: H01M50/171 ,  H01M10/0585 ,  H01M50/191 ,  H01M50/197 ,  H01M50/186

Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.

公开(公告)号：US11101513B2

公开(公告)日：2021-08-24

申请号：US16121307

申请日：2018-09-04

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Bing Dang ,  Bo Wen ,  Marlon Agno ,  John Knickerbocker

IPC: H01M50/116 ,  H01M10/0585 ,  H01M50/124 ,  H01M50/183

Abstract: Techniques regarding a thin film battery, which can comprise one or more sealing layers, and a method of manufacturing thereof are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a thin film battery cell encapsulated in a multi-layer stack comprising an adhesive layer located between a first substrate layer and a second substrate layer. The apparatus can also comprise a metal sealing layer at least partially surrounding the multi-layer stack.

公开(公告)号：US10784380B2

公开(公告)日：2020-09-22

申请号：US16686643

申请日：2019-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zheng Xu ,  Zhenxing Bi ,  Dexin Kong ,  Qianwen Chen

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device including a gate-all-around based non-volatile memory device includes isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels, at least one floating gate including a first gate material encapsulating the isolated channels, and at least one control gate including a second gate material encapsulating the isolated channels.

公开(公告)号：US20200051948A1

公开(公告)日：2020-02-13

申请号：US16658675

申请日：2019-10-21

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Bing Dang ,  Russell Budd ,  Bo Wen ,  Li-Wen Hung ,  Jae-Woong Nah ,  John Knickerbocker

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/683

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

公开(公告)号：US10361140B2

公开(公告)日：2019-07-23

申请号：US15178709

申请日：2016-06-10

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Bing Dang ,  John Knickerbocker ,  Joana Sofia Branquinho Teresa Maria

IPC: H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065

Abstract: A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors.

公开(公告)号：US20180220910A1

公开(公告)日：2018-08-09

申请号：US15424265

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Huan Hu ,  Zheng Xu ,  Xin Zhang

IPC: A61B5/0408 ,  A61B5/0478 ,  A61B5/0496 ,  A61B5/0492 ,  A61B5/00

CPC classification number: A61B5/0408 ,  A61B5/0478 ,  A61B5/0492 ,  A61B5/0496 ,  A61B5/685 ,  A61B2562/0209 ,  A61B2562/0285 ,  A61B2562/125

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

公开(公告)号：US20180212424A1

公开(公告)日：2018-07-26

申请号：US15804605

申请日：2017-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Yang Liu ,  Dongbing Shao ,  Zheng Xu

IPC: H02H9/04

Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.

公开(公告)号：US20170358554A1

公开(公告)日：2017-12-14

申请号：US15178709

申请日：2016-06-10

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Bing Dang ,  John Knickerbocker ,  Joana Sofia Branquinho Teresa Maria

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3142 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81065 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01026

Abstract: A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors.