-
公开(公告)号：US11877524B2
公开(公告)日：2024-01-16
申请号：US17469203
申请日：2021-09-08
发明人： Juntao Li , Kangguo Cheng , Dexin Kong , Zheng Xu
IPC分类号： H10N70/00
CPC分类号： H10N70/063 , H10N70/826 , H10N70/8833 , H10N70/021
摘要： Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.
-
公开(公告)号：US20230144050A1
公开(公告)日：2023-05-11
申请号：US17519924
申请日：2021-11-05
发明人： Dexin Kong , Kangguo Cheng , Juntao Li , Zheng Xu
IPC分类号： H01L45/00
CPC分类号： H01L45/1691 , H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/144
摘要： Semiconductor devices and methods for forming the semiconductor devices are described. An example semiconductor structure can include a substrate including a first electrode. The example semiconductor structure can further include a heater element directly contacting the first electrode in the substrate. The example semiconductor structure a phase change cell directly on the heater element. The sidewalls of the phase change cell can be encapsulated with a spacer. The example semiconductor structure a second electrode directly on the phase change cell and the spacer.
-
公开(公告)号：US20220181154A1
公开(公告)日：2022-06-09
申请号：US17677469
申请日：2022-02-22
发明人： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC分类号： H01L21/033 , H01L23/528 , H01L21/768 , H01L21/311
摘要： A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
-
公开(公告)号：US11058337B2
公开(公告)日：2021-07-13
申请号：US15424265
申请日：2017-02-03
发明人： Qianwen Chen , Huan Hu , Zheng Xu , Xin Zhang
摘要： A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.
-
公开(公告)号：US10930734B2
公开(公告)日：2021-02-23
申请号：US16174603
申请日：2018-10-30
发明人： Ruqiang Bao , Zhenxing Bi , Kangguo Cheng , Zheng Xu
IPC分类号： H01L29/06 , H01L29/08 , H01L21/762 , H01L21/02
摘要： A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
-
公开(公告)号：US10915690B2
公开(公告)日：2021-02-09
申请号：US16383326
申请日：2019-04-12
发明人： Dongbing Shao , Yongan Xu , Shyng-Tsong Chen , Zheng Xu
IPC分类号： G06F30/30 , G06F30/398
摘要： Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.
-
公开(公告)号：US10804274B2
公开(公告)日：2020-10-13
申请号：US16286843
申请日：2019-02-27
发明人： Zhenxing Bi , Zheng Xu , Dexin Kong , Kangguo Cheng
IPC分类号： H01L21/44 , H01L27/105 , H01L21/8229 , H01L29/06
摘要： A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
-
公开(公告)号：US10790271B2
公开(公告)日：2020-09-29
申请号：US15954819
申请日：2018-04-17
发明人： Zheng Xu , Chen Zhang , Ruqiang Bao , Dongbing Shao
摘要： A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.
-
公开(公告)号：US10608121B2
公开(公告)日：2020-03-31
申请号：US15846445
申请日：2017-12-19
发明人： Ruqiang Bao , Zhenxing Bi , Kangguo Cheng , Zheng Xu
IPC分类号： H01L29/788 , H01L29/78 , H01L29/06 , H01L29/49 , H01L29/66 , H01L29/417 , H01L21/28
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
-
公开(公告)号：US20200098863A1
公开(公告)日：2020-03-26
申请号：US16684022
申请日：2019-11-14
发明人： Zhenxing Bi , Kangguo Cheng , Peng Xu , Zheng Xu
IPC分类号： H01L29/08 , H01L21/8234 , H01L29/786 , H01L27/088 , H01L29/78
摘要： A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
-
-
-
-
-
-
-
-
-
搜索结果
105 条记录 (耗时 0.028 秒)
