公开(公告)号：US07539042B2

公开(公告)日：2009-05-26

申请号：US11783318

申请日：2007-04-09

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10829

摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit for generating a back bias potential based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.

摘要翻译： 本发明抑制由于MOSFET的阈值的偏差引起的DRAM的刷新故障。 DRAM具有第一单元，用于记录要施加到单元晶体管的背栅的背偏置电位的设定值，以及用于产生背偏电位的第二单元，其基于记录在所述单元晶体管中的背偏电位的设定值 第一单元并将所产生的反向偏置电位提供给所述后栅极，其中当具有与所述单元晶体管相同的并且已经以与所述单元晶体管相同的工艺制造的结构的MOSFET的阈值大于目标值时， 单元晶体管应当具有比目标值的背偏电位浅的值被记录在第二单元中。

公开(公告)号：US07109775B2

公开(公告)日：2006-09-19

申请号：US11110685

申请日：2005-04-21

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K2005/00071

摘要： A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input signal when the capacitor is to be charged with electric charge; a second switch (102) connected to the input signal line and operating according to the input signal when the electric charge is to be discharged from the capacitor; and a comparison circuit (107) comparing a voltage of the capacitor and a reference voltage to output a delay signal of the input signal.

摘要翻译： 延迟电路包括：输入信号线（IN），输入信号经输入信号线输入; 充电并放电的电容器（106） 第一开关（101），连接到所述输入信号线，并且当所述电容器要被充电时根据所述输入信号进行操作; 第二开关（102），连接到输入信号线，并且当电荷从电容器放电时，根据输入信号进行操作; 以及将电容器的电压和参考电压进行比较以输出输入信号的延迟信号的比较电路（107）。

公开(公告)号：US06973001B1

公开(公告)日：2005-12-06

申请号：US11036393

申请日：2005-01-18

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/037 ,  H03K3/356 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/133 ,  H03K2005/00234

摘要： The gates of each pair of second transistors receive a pair of delayed timing signals whose rising and falling edges are adjacent to each other, respectively, and gradually discharge the charges at a first node pre-charged to a first power supply voltage. The discharge speed varies depending on the threshold voltage, operating temperature, and power supply voltage of the transistors. A plurality of detection circuits operates at timings different from each other to detect the voltage at the first node as logic values. A selector selects any one of the second timing signals depending on a detection result provided by the detection circuit. An internal circuit operates in synchronization with the second timing signal selected. Accordingly, the operation timing of the internal circuit can be optimally adjusted in response to a change in operating environments. This allows the improvement in operation margin of the semiconductor integrated circuit.

摘要翻译： 每对第二晶体管的栅极分别接收一对延迟定时信号，其上升沿和下降沿分别相邻，并且将预充电的第一节点处的电荷逐渐放电至第一电源电压。 放电速度根据晶体管的阈值电压，工作温度和电源电压而变化。 多个检测电路在彼此不同的定时运行，以将第一节点处的电压检测为逻辑值。 选择器根据由检测电路提供的检测结果来选择第二定时信号中的任何一个。 内部电路与所选择的第二定时信号同步工作。 因此，可以根据操作环境的变化来最佳地调整内部电路的操作定时。 这允许改善半导体集成电路的操作裕度。

公开(公告)号：US06671787B2

公开(公告)日：2003-12-30

申请号：US09264672

申请日：1999-03-09

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C7/1087 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C29/14

摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

摘要翻译： 本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有 传输类型与外部时钟的上升沿和下降沿同步传输数据。 半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。 此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

公开(公告)号：US06373783B1

公开(公告)日：2002-04-16

申请号：US09587296

申请日：2000-06-05

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C8/18

摘要： In performing a read operation or a write operation in a memory cell, a row control circuit is first operated to activate a word line. Subsequently, a command control circuit receives a column operation command in synchronization with a clock signal so as to operate a column control circuit. Here, under the control of a timing adjusting circuit, the column control circuit starts operating a predetermined delay time after the reception of the column operation command. By delaying the operation of the column control circuit, the read operation or the write operation in the memory cell can be performed at the optimum timing corresponding to the operating timing of an internal circuit independent of the cycle of the clock signal. As a result, the number of times in receiving commands per unit time can be increased to enhance the bus occupation rate of data. Since the column control circuit is operated at the optimum timing corresponding to the operating timing of the internal circuit, a read cycle time and a write cycle time can be shortened.

公开(公告)号：US06288585B1

公开(公告)日：2001-09-11

申请号：US09535745

申请日：2000-03-27

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

公开(公告)号：US06252804B1

公开(公告)日：2001-06-26

申请号：US09629619

申请日：2000-07-31

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C1140

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078

摘要： A semiconductor integrated circuit comprising memory cells and a holding unit. The holding unit holds write data to the memory cell and mask information for masking a predetermined bit or bits of the write data, both supplied corresponding to a write command, as held write data and held mask information. On receiving a next write command, the semiconductor integrated circuit masks held write data in accordance with held mask information and writes the resultant to the memory cell. The holding unit holds next write data and next mask information supplied corresponding to this write command as held write data and held mask information. That is, the held write data and the held mask information are rewritten. Thereby, the semiconductor integrated circuit which writes write data previously accepted upon the reception of a next write command can mask the write data.

摘要翻译： 一种包括存储单元和保持单元的半导体集成电路。 保持单元将写入数据保存到存储单元，并且掩蔽信息，用于屏蔽对应于写入命令的写入数据的预定位或位，作为保持写入数据和保持的掩码信息。 在接收到下一个写入命令时，半导体集成电路根据所保持的掩码信息掩蔽保持写入数据，并将结果写入存储单元。 保持单元保持与该写入命令相对应的下一个写入数据和下一个掩模信息作为保持的写入数据和保持的掩码信息。 也就是说，保持的写入数据和保持的掩码信息被重写。 由此，在接收下一个写入命令时写入预先接受的写入数据的半导体集成电路可以掩蔽写入数据。

公开(公告)号：US06064625A

公开(公告)日：2000-05-16

申请号：US1460

申请日：1997-12-31

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C29/84 ,  G11C7/1039 ,  G11C7/22 ,  G11C2207/229

摘要： The present invention internally latches a write data signal applied in synchronous with an external data strobe signal in response to an internal data strobe signal which is generated in response to this external data strobe signal, and furthermore, supplies the write data signal to a memory cell array from a write circuit such as a write amplifier in response to a write signal generated from this external data strobe signal. Meanwhile, an address signal is introduced internally in accordance with an external clock. Therefore, since the driving of the data bus connected to a memory cell array from a write amplifier, which constitutes a write operation internal to memory, commences in accordance with an external data strobe signal, a write operation can be ended in the shortest possible time from write data signal input. The above-described invention is especially effective when memory comprises a 2-bit pre-fetch. That is, a 2-bit write data signal is supplied time-sequentially in synchronous with an external data strobe signal. Since an internal write operation can commence after receiving for the input of that second write data signal, it enables the shortest write operation.

摘要翻译： 本发明响应于响应于该外部数据选通信号而产生的内部数据选通信号，内部锁存与外部数据选通信号同步施加的写入数据信号，此外，将写入数据信号提供给存储单元 响应于从该外部数据选通信号产生的写入信号，写入诸如写放大器的写入电路的阵列。 同时，根据外部时钟在内部引入地址信号。 因此，由于构成存储器内部的写操作的写放大器连接到存储单元阵列的数据总线的驱动根据外部数据选通信号开始，所以可以在最短的时间内结束写入操作 从写数据信号输入。 当存储器包括2位预取时，上述发明特别有效。 也就是说，与外部数据选通信号同步地按时间顺序地提供2位写入数据信号。 由于在接收到该第二写入数据信号的输入之后可以开始内部写入操作，所以能够进行最短的写入操作。

公开(公告)号：US5751652A

公开(公告)日：1998-05-12

申请号：US867044

申请日：1997-06-02

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C5/143 ,  G11C5/147 ,  G05F1/465

摘要： A semiconductor apparatus includes a voltage unit which supplies a down voltage produced at a node, the voltage unit having a plurality of resistors connected in series between a power supply line and a grounding line, the node being a connection point between the plurality of resistors. A backup unit pulls up the node of the voltage unit when a voltage at the node is below a lower limit of the down voltage, so that the voltage at the node increases to the lower limit, and pulls down the node of the voltage unit when the voltage at the node is above an upper limit of the down voltage, so that the voltage at the node decreases to the upper limit. A control unit sets the backup unit in one of an active state and an inactive state in response to a control signal.

摘要翻译： 半导体装置包括提供在节点处产生的降压的电压单元，所述电压单元具有串联连接在电源线和接地线之间的多个电阻器，所述节点是所述多个电阻器之间的连接点。 当节点电压低于下降电压的下限时，备用单元拉电压单元的节点，使得节点处的电压上升到下限，并将电压单元的节点拉低 节点处的电压高于降压的上限，使得节点处的电压下降到上限。 控制单元响应于控制信号将备份单元设置为活动状态和非活动状态之一。

公开(公告)号：US5592433A

公开(公告)日：1997-01-07

申请号：US643834

申请日：1996-05-07

申请人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

发明人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

IPC分类号： G11C7/06 ,  G11C13/00

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

摘要翻译： 一种半导体存储器件包括其中提供多个读出放大器的存储单元阵列，多个分段驱动线，每个驱动线连接到用于驱动读出放大器的一组读出放大器，每个分段驱动线由第一和第二 形成一对的驱动线段和用于向分段驱动线提供电力的多个中继线。 每个中继线包括从存储单元阵列的第一侧向第二侧延伸的第一导体条，用于在与第一驱动线段交叉时与多个第一驱动线段连接，第二导体条从第二侧延伸 所述存储单元阵列朝向所述第一侧，用于在与所述第二驱动线段交叉时连接到所述第二驱动线段。 第一和第二导体条具有具有减小的宽度和相互互补形状的远端部分，使得第一和第二导体条被设置成形成整个存储单元阵列具有基本恒定的宽度的直条。