公开(公告)号：US12272659B2

公开(公告)日：2025-04-08

申请号：US17944596

申请日：2022-09-14

Applicant: Applied Materials, Inc.

Inventor： Yi Xu ,  Yu Lei ,  Zhimin Qi ,  Aixi Zhang ,  Xianyuan Zhao ,  Wei Lei ,  Xingyao Gao ,  Shirish A. Pethe ,  Tao Huang ,  Xiang Chang ,  Patrick Po-Chun Li ,  Geraldine Vasquez ,  Dien-yeh Wu ,  Rongjun Wang

IPC: H01L23/00

Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

公开(公告)号：US12272521B2

公开(公告)日：2025-04-08

申请号：US18199780

申请日：2023-05-19

Applicant: Applied Materials, Inc.

Inventor： Vladimir Nagorny ,  Wei Liu ,  Rene George

IPC: H01J37/32

Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.

公开(公告)号：US20250113522A1

公开(公告)日：2025-04-03

申请号：US18899327

申请日：2024-09-27

Applicant: Applied Materials, Inc.

Inventor： Ruiying HAO ,  Fredrick David FISHBURN ,  Raghuveer Satya MAKALA ,  Thomas John KIRSCHENHEITER ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/775 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Three-dimensional (3D) memory structures and methods of formation of same are provided herein. In some embodiments, a 3D memory fabrication structure includes: a base silicon (Si) layer; a silicon germanium (SiGe) layer disposed above the base Si layer; and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant that is at least one of carbon (C) or boron (B).

公开(公告)号：US20250112091A1

公开(公告)日：2025-04-03

申请号：US18899407

申请日：2024-09-27

Applicant: Applied Materials, Inc.

Inventor： Jianqiu GUO ,  Dong WANG ,  Liqi WU ,  Yiyang WAN ,  Shumao ZHANG ,  Qihao ZHU ,  Weifeng YE ,  Jiang LU ,  Shihchung CHEN

IPC: H01L21/768 ,  C23C16/02 ,  C23C16/42 ,  C23C16/455 ,  H01J37/32 ,  H01L21/285 ,  H01L23/532

Abstract: A contact structure includes a cavity comprising a device contact formed on a surface of a substrate, a bottom surface, and sidewalls. A metal silicide layer disposed over the surface of the device contact, the bottom surface, and the sidewalls of the cavity, and a treated surface formed over a portion of the metal silicide layer disposed over the sidewalls of the cavity.

公开(公告)号：US20250112054A1

公开(公告)日：2025-04-03

申请号：US18894665

申请日：2024-09-24

Applicant: Applied Materials, Inc.

Inventor： Yuriy Shusterman ,  Sean Reidy ,  Sai Hooi Yeong ,  Lisa Megan McGill ,  Benjamin Colombeau ,  Andre P. Labonte ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/26 ,  H01L21/311

Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

公开(公告)号：US20250108476A1

公开(公告)日：2025-04-03

申请号：US18977686

申请日：2024-12-11

Applicant: Applied Materials, Inc.

Inventor： Haosheng Wu ,  Hari Soundararajan ,  Yen-Chu Yang ,  Jianshe Tang ,  Shou-Sung Chang ,  Shih-Haur Shen ,  Taketo Sekine

IPC: B24B37/015 ,  B24B37/10 ,  B24B49/02 ,  B24B49/04 ,  B24B49/14 ,  B24B55/02 ,  B24B57/02

Abstract: A chemical mechanical polishing system includes a support to hold a polishing pad, a carrier head to hold a substrate against the polishing pad during a polishing process, an in-situ monitoring system configured to generate a signal indicative of an amount of material on the substrate, a temperature control system to control a temperature of the polishing process, and a controller coupled to the in-situ monitoring system and the temperature control system. The controller is configured to cause the temperature control system to vary the temperature of the polishing process in response to the signal.

公开(公告)号：US12266560B2

公开(公告)日：2025-04-01

申请号：US17832775

申请日：2022-06-06

Applicant: Applied Materials, Inc.

Inventor： Kin Pong Lo ,  Vladimir Nagorny ,  Wei Liu ,  Theresa Kramer Guarini ,  Bernard L. Hwang ,  Malcolm J. Bevan ,  Jacob Abraham ,  Swayambhu Prasad Behera

IPC: H01L21/687 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L21/67

Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.

公开(公告)号：US12265380B2

公开(公告)日：2025-04-01

申请号：US17137679

申请日：2020-12-30

Applicant: Applied Materials, Inc.

Inventor： James Robert Moyne ,  Jimmy Iskandar

IPC: G03F7/00 ,  F27B17/00 ,  G05B13/04 ,  G05B19/418 ,  H01L21/66 ,  H01L21/67 ,  H05K3/00 ,  C23C16/00

Abstract: A method includes identifying first parameters of a first processing chamber of a semiconductor fabrication facility. The first parameters include first input parameters and first output parameters. The method further includes identifying second parameters of a second processing chamber of the semiconductor fabrication facility. The second parameters include second input parameters and second output parameters. The method further includes generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters and composite output parameters. Semiconductor fabrication is based on the composite parameters.

公开(公告)号：US20250107353A1

公开(公告)日：2025-03-27

申请号：US18977548

申请日：2024-12-11

Applicant: Applied Materials, Inc.

Inventor： Chung-Chia CHEN ,  Ji Young CHOUNG ,  Dieter HAAS ,  Yu-Hsin LIN ,  Jungmin LEE ,  Wen-Hao WU ,  Si Kyoung KIM

IPC: H10K59/122 ,  H10K59/173 ,  H10K59/80

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one example, a device includes a substrate, pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality of overhang structures. The first sub-pixel includes a first anode, OLED material, a first cathode, and a first encapsulation layer having a gap defined by a first portion of the first encapsulation layer disposed over the first cathode, a second portion of the first encapsulation layer disposed over a sidewall of the body structure, and a third portion of the first encapsulation layer under an underside surface of the top extension of the top structure, the first portion of the first encapsulation layer contacting the third portion of the first encapsulation layer.

公开(公告)号：US20250107068A1

公开(公告)日：2025-03-27

申请号：US18886692

申请日：2024-09-16

Applicant: Applied Materials, Inc.

Inventor： Tong LIU ,  Sony VARGHESE ,  Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B12/00 ,  H01L21/762

Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.