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    Memory devices having contact features
    41.
    发明授权
    Memory devices having contact features 有权
    具有接触特征的存储器件

    公开(公告)号：US08076783B2

    公开(公告)日：2011-12-13

    申请号：US12392886

    申请日：2009-02-25

    Applicant: Steven T. Harshfield

    Inventor： Steven T. Harshfield

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

    Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

    Abstract translation: 描述了环状，线性和点接触结构，其显示出比常规圆形接触插塞大大降低由光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。

    Phase change memory device and method for manufacturing the same
    42.
    发明授权
    Phase change memory device and method for manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US08058637B2

    公开(公告)日：2011-11-15

    申请号：US12346306

    申请日：2008-12-30

    Applicant: Ki Bong Nam

    Inventor： Ki Bong Nam

    IPC: H01L29/02

    CPC classification number: H01L27/1021 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  Y10S257/91

    Abstract: A phase change memory device includes a semiconductor substrate having a first conductivity type well An isolation structure is formed in the semiconductor substrate having the first conductivity type well to define active regions. Second conductivity type high concentration areas are formed in surfaces of the active regions. Insulation patterns are formed under the second conductivity type high concentration areas to insulate the second conductivity type high concentration areas from the first conductivity type well. A plurality of vertical diodes are formed on the second conductivity type high concentration areas which are insulated from the first conductivity type well.

    Abstract translation: 相变存储器件包括具有第一导电型阱的半导体衬底。在具有第一导电类型的半导体衬底中形成隔离结构以形成有源区。 在活性区域的表面形成第二导电型高浓度区域。 在第二导电型高浓度区域下形成绝缘图案，以将第二导电类型的高浓度区域与第一导电类型阱绝缘。 在与第一导电型阱绝缘的第二导电型高浓度区域上形成多个垂直二极管。

    Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same
    43.
    发明授权
    Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same 有权
    过程变异耐受二极管，包括相同的标准单元，标签和包含其的传感器及其制造方法

    公开(公告)号：US07932537B2

    公开(公告)日：2011-04-26

    申请号：US12424509

    申请日：2009-04-15

    Applicant: Vivek Subramanian ,  Patrick Smith

    Inventor： Vivek Subramanian ,  Patrick Smith

    IPC: H01L29/70

    CPC classification number: H01L29/86 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  Y10S257/91 ,  Y10T307/964

    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

    Abstract translation: 公开了包含这种二极管和TFT的工艺变容二极管和二极管连接的薄膜晶体管（TFT），印刷或图案化结构（例如电路），其制造方法及其用于识别标签和传感器的应用。 包括串联的互补二极管或二极管连接的TFT的图案化结构可以稳定使用印刷或激光写入技术制造的二极管的阈值电压（Vt）。 本发明有利地利用NMOS TFT（Vtn）的Vt和PMOS TFT（Vtp）的Vt之间的间隔来建立和/或提高印刷或激光写入的二极管上的正向压降的稳定性。 本发明的其它应用涉及参考电压发生器，电压钳位电路，控制相关或差分信号传输线上的电压的方法，以及RFID和EAS标签和传感器。

    Semiconductor device
    44.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07909260B2

    公开(公告)日：2011-03-22

    申请号：US12638090

    申请日：2009-12-15

    Applicant: Jun Koyama ,  Shunpei Yamazaki

    Inventor： Jun Koyama ,  Shunpei Yamazaki

    IPC: G06K19/06 ,  G06K7/08

    CPC classification number: G06K19/07345 ,  Y10S257/91

    Abstract: A semiconductor device used as an ID chip is provided, of which operation is terminated when its role is finished or expires. According to the invention, an antenna circuit, a voltage detecting circuit, a current amplifier circuit, a signal processing circuit, and a fuse are provided over an insulating substrate. When large power is applied to the antenna circuit, a voltage is detected by voltage detecting circuit and a corresponding current is amplified by the current amplifier circuit, thereby the fuse is melted down. Also, when an anti-fuse is used, the anti-fuse can short an insulating film by applying an excessive voltage. In this manner, the semiconductor device has a function for making it invalid by stopping operation of the signal processing circuit when the role of the device is finished or expires.

    Abstract translation: 提供了用作ID芯片的半导体器件，当其作用完成或到期时，其操作终止。 根据本发明，在绝缘基板上设置天线电路，电压检测电路，电流放大电路，信号处理电路和保险丝。 当对天线电路施加大功率时，由电压检测电路检测电压，并且由电流放大器电路对相应的电流进行放大，从而熔断熔断器。 此外，当使用抗熔丝时，抗熔丝可能通过施加过大的电压而使绝缘膜短路。 以这种方式，当装置的作用完成或到期时，半导体装置具有通过停止信号处理电路的操作使其无效的功能。

    Reducing leakage currents in memories with phase-change material
    45.
    发明授权
    Reducing leakage currents in memories with phase-change material 有权
    通过相变材料降低存储器中的漏电流

    公开(公告)号：US07906391B2

    公开(公告)日：2011-03-15

    申请号：US11272308

    申请日：2005-11-10

    Applicant: Daniel Xu ,  Tyler A. Lowery

    Inventor： Daniel Xu ,  Tyler A. Lowery

    IPC: H01L21/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/144 ,  Y10S257/91

    Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.

    Abstract translation: 包括相变材料的存储单元可能具有减小的漏电流。 在一个实施例中，小区可以通过掩埋字线接收信号。 掩埋字线可以包括在较重掺杂的N型区域上的更重掺杂的N型区域上的更轻掺杂的N型区域的夹层。 作为形成掩埋字线的N型区域的结构的结果，可以显着地减少掩埋字线在反向偏压条件下对衬底的漏电流。

    Arrangements of fuse-type constructions
    46.
    发明授权
    Arrangements of fuse-type constructions 有权
    保险丝型结构的安排

    公开(公告)号：US07772680B2

    公开(公告)日：2010-08-10

    申请号：US11207116

    申请日：2005-08-18

    Applicant: H. Montgomery Manning

    Inventor： H. Montgomery Manning

    IPC: H01L23/58 ,  H01L23/62

    CPC classification number: H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S257/91 ,  H01L2924/00

    Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

    Abstract translation: 本发明包括在多个导电连接件上并与之电接触的包含导电板的半导体熔丝装置。 每个链接件相对于其它连接件与导电板接触作为一个单独的区域，并且链接件与导电板接触的区域是熔丝。 本发明还包括形成半导体熔丝装置的方法。

    PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    47.
    发明申请
    PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    相变存储器件及其制造方法

    公开(公告)号：US20100117043A1

    公开(公告)日：2010-05-13

    申请号：US12346306

    申请日：2008-12-30

    Applicant: Ki Bong NAM

    Inventor： Ki Bong NAM

    IPC: H01L47/00 ,  G11C11/00 ,  H01L31/20

    CPC classification number: H01L27/1021 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  Y10S257/91

    Abstract: A phase change memory device includes a semiconductor substrate having a first conductivity type well An isolation structure is formed in the semiconductor substrate having the first conductivity type well to define active regions. Second conductivity type high concentration areas are formed in surfaces of the active regions. Insulation patterns are formed under the second conductivity type high concentration areas to insulate the second conductivity type high concentration areas from the first conductivity type well. A plurality of vertical diodes are formed on the second conductivity type high concentration areas which are insulated from the first conductivity type well.

    Abstract translation: 相变存储器件包括具有第一导电型阱的半导体衬底。在具有第一导电类型的半导体衬底中形成隔离结构以形成有源区。 在活性区域的表面形成第二导电型高浓度区域。 在第二导电型高浓度区域下形成绝缘图案，以将第二导电类型的高浓度区域与第一导电类型阱绝缘。 在与第一导电型阱绝缘的第二导电型高浓度区域上形成多个垂直二极管。

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