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公开(公告)号：US20180013345A1
公开(公告)日：2018-01-11
申请号：US15546828
申请日：2016-01-29
申请人： AutoNetworks Technologies, Ltd. , Sumitomo Wiring Systems, Ltd. , SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Yutaka Kakuno
CPC分类号： H02M3/157 , F02D41/20 , G05F1/00 , H02M7/48 , H02M2001/0009 , H03M1/0609
摘要： As paths for a current flowing through a conductor, a first current path through which a current flows from a first conductive portion to a second conductive portion, and a second current path through which a current flows from a third conductive portion to the second conductive portion are provided. Each of the first conductive portion, the second conductive portion, and the third conductive portion has a plate shape, a point P1 is located on a plate surface of the first conductive portion, and a point P2 is located on a plate surface of the second conductive portion. A current detecting circuit detects a value related to a potential difference between the points P1 and P2, and outputs a voltage value corresponding to a values of a current flowing through each of the first current path and the second current path.
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42.发明申请公开(公告)号：US20170250698A9
公开(公告)日：2017-08-31
申请号：US14939473
申请日：2015-11-12
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Hao Liu
CPC分类号： H03M1/0609 , H03M1/0607 , H03M1/0682 , H03M1/1245 , H03M1/442 , H03M1/468
摘要： Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single switched capacitors per input line.
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公开(公告)号：US09680494B2
公开(公告)日：2017-06-13
申请号：US14506485
申请日：2014-10-03
发明人： Seiji Hashimoto , Takeru Suzuki , Yasushi Matsuno , Takashi Muto
CPC分类号： H03M1/0609 , H03M1/1019 , H03M1/123 , H03M1/186 , H03M1/56 , H04N5/225 , H04N5/3355 , H04N5/378
摘要： When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.
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公开(公告)号：US20170155398A1
公开(公告)日：2017-06-01
申请号：US14954577
申请日：2015-11-30
发明人： Sriram NARAYANAN , Srinath RAMASWAMY , Arup POLLEY , Ajit SHARMA
CPC分类号： H03M1/0609 , H03M1/001 , H03M1/002 , H03M1/1295 , H03M1/162
摘要： An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.
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45.发明授权Apparatus for gain selection with compensation for parasitic elements and associated methods 有权用于增益选择的装置，用于补偿寄生元件和相关方法公开(公告)号：US09515671B1
公开(公告)日：2016-12-06
申请号：US14732701
申请日：2015-06-06
CPC分类号： H03M1/0607 , H03K5/003 , H03M1/00 , H03M1/002 , H03M1/0609 , H03M1/66 , H03M1/664 , H03M1/682 , H03M1/747 , H03M1/808
摘要： Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.
摘要翻译： 公开了用于利用寄生元件补偿进行增益编程或选择的装置和相关方法。 在一个示例性实施例中，装置包括具有第一可编程增益的第一电路，并且包括具有寄生元件的第一组分量。 该装置还包括具有第二可编程增益的第二电路，并且包括具有寄生元件的第二组分量。 该装置具有作为第一和第二可编程增益的乘积的增益。 通过将第一可编程增益设置为第二可编程增益的倒数来消除由于第一和第二组分组的寄生元件引起的增益误差。
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公开(公告)号：US20160315629A1
公开(公告)日：2016-10-27
申请号：US14871373
申请日：2015-09-30
CPC分类号： H03M1/0609 , H03M1/203 , H03M1/361
摘要： In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
摘要翻译： 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。
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公开(公告)号：US09306589B1
公开(公告)日：2016-04-05
申请号：US14503585
申请日：2014-10-01
申请人： Spansion LLC
发明人： Tetsuro Okura , Yusaku Ito , Hirohiko Sadamatsu
CPC分类号： H03M1/0609 , H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/372 , H03F2203/45551 , H03F2203/45634 , H03M1/0626 , H03M1/124
摘要： An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit.
摘要翻译： 模拟数字转换系统包括模数转换器; 以及前置放大器电路，其被提供在模拟数字转换器的前一级并差分地放大输入的模拟信号。 在前置放大器电路中，发生偏移电压和/或噪声和/或混合。 前置放大器电路输出两种类型的模拟放大差分信号，其中仅相对于偏移电压和/或噪声反相。 模拟数字转换器具有平均电路，其对模数转换之前的采样的每个时钟周期对两种类型的模拟放大差分信号进行平均，并且基于由平均电路平均的差分信号输出数字信号。
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公开(公告)号：US09100034B2
公开(公告)日：2015-08-04
申请号：US14203052
申请日：2014-03-10
发明人： Takashi Oshima , Tatsuji Matsuura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto , Keisuke Kimura
CPC分类号： H03M1/1245 , H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1038 , H03M1/109 , H03M1/14 , H03M1/38 , H03M1/44 , H03M1/46 , H03M1/56
摘要： A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
摘要翻译： 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。
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49.发明授权公开(公告)号：US08947281B1
公开(公告)日：2015-02-03
申请号：US14209725
申请日：2014-03-13
CPC分类号： H03M1/66 , H03M1/0609
摘要： Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.
摘要翻译： 公开了用于数模转换的装置和方法。 在一个实施例中，电子系统包括偏置电路和数模转换器（DAC），数字 - 模拟转换器（DAC）包括接收数字输入信号的输入和驱动传输线的输出。 数字输入信号可用于控制DAC的输出电流的幅度和极性。 DAC还包括从偏置电路接收第一偏置电压的一个或多个p型金属氧化物半导体（PMOS）终端晶体管，以及一个或多个从第二偏置电压接收第二偏置电压的n型金属氧化物半导体（NMOS） 偏置电路。 偏置电路控制第一和第二偏置电压的电压电平以控制端接晶体管的小信号电阻以主动地终止DAC的输出。
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50.发明申请INTEGRATED CIRCUIT, ANALOG-DIGITAL CONVERTER AND CMOS IMAGE SENSOR WITH THE SAME 有权集成电路，模拟数字转换器和CMOS图像传感器公开(公告)号：US20140346320A1
公开(公告)日：2014-11-27
申请号：US14049994
申请日：2013-10-09
申请人： SK hynix Inc.
发明人： Young-Chul SOHN
摘要： A integrated circuit includes an analog power domain circuit having more than one stages, a digital power domain circuit having at least one stage receiving the output signal of the analog power domain circuit, and a voltage regulating unit suitable for supplying at least one scaled power to the latter part of the stages to reduce a voltage level difference between the analog power domain circuit and the digital power domain circuit.
摘要翻译： 集成电路包括具有多于一个级的模拟功率域电路，具有至少一个级的数字功率域电路，其接收模拟功率域电路的输出信号，以及电压调节单元，适于将至少一个缩放的功率提供给 后期部分降低模拟功率域电路与数字电源电路之间的电压电平差。
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