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公开(公告)号：US11664814B2
公开(公告)日：2023-05-30
申请号：US17461400
申请日：2021-08-30
CPC分类号： H03M1/203 , G06G7/30 , H03F3/45183 , H03M1/365
摘要： Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.
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公开(公告)号：US20170085820A1
公开(公告)日：2017-03-23
申请号：US15311701
申请日：2015-05-27
申请人： SONY CORPORATION
发明人： YOSHIAKI INADA
CPC分类号： H04N5/378 , H03M1/08 , H03M1/123 , H03M1/203 , H03M1/56 , H04N5/363 , H04N5/3698 , H04N5/374 , H04N5/37455
摘要： The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method which enable achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings. The present technology can be applied to, for example, an ADC that performs AD conversion for an electrical signal output from a pixel.
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3.发明授权Quantizer with sigma-delta modulator, analog-to-digital converter including the same and quantization method using the same 有权具有Σ-Δ调制器的量化器，包括相同的模数转换器和使用其的量化方法公开(公告)号：US09054738B2
公开(公告)日：2015-06-09
申请号：US14286699
申请日：2014-05-23
发明人： Junsoo Cho , Hyunjoong Lee , Suhwan Kim
摘要： The present invention provides a quantizer with a sigma-delta modulator, an analog-to-digital converter including the same and a quantization method using the same capable of obtaining a high signal-to-noise ratio with a relatively small number of comparators. The quantizer, the analog-to-digital converter and the quantization method of the present invention reduces quantization errors and increases noise shaping order.
摘要翻译： 本发明提供了一种具有Σ-Δ调制器的量化器，包括该Σ-Δ调制器的模数转换器和使用该Σ-Δ调制器的量化器，该量化方法能够以相对较少数量的比较器获得高信噪比。 本发明的量化器，模数转换器和量化方法降低了量化误差并增加了噪声整形次序。
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4.发明申请QUANTIZER WITH SIGMA-DELTA MODULATOR, ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME AND QUANTIZATION METHOD USING THE SAME 有权具有SIGMA-DELTA调制器的量化器，包括其的模拟数字转换器和使用其的量化方法公开(公告)号：US20140347200A1
公开(公告)日：2014-11-27
申请号：US14286699
申请日：2014-05-23
发明人： Junsoo CHO , Hyunjoong LEE , Suhwan KIM
摘要： The present invention provides a quantizer with a sigma-delta modulator, an analog-to-digital converter including the same and a quantization method using the same capable of obtaining a high signal-to-noise ratio with a relatively small number of comparators. The quantizer, the analog-to-digital converter and the quantization method of the present invention reduces quantization errors and increases noise shaping order.
摘要翻译： 本发明提供了一种具有Σ-Δ调制器的量化器，包括该Σ-Δ调制器的模数转换器和使用该Σ-Δ调制器的量化器，该量化方法能够以相对较少数量的比较器获得高信噪比。 本发明的量化器，模数转换器和量化方法降低了量化误差并增加了噪声整形次序。
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5.发明申请INTERPOLATION CIRCUIT, RECEPTION CIRCUIT AND METHOD OF GENERATING INTERPOLATED DATA 有权插值电路，接收电路和产生插值数据的方法公开(公告)号：US20130278294A1
公开(公告)日：2013-10-24
申请号：US13827726
申请日：2013-03-14
申请人： FUJITSU LIMITED
发明人： Takayuki SHIBASAKI
IPC分类号： H03K5/00
摘要： An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.
摘要翻译： 内插电路包括：生成电路，被配置为基于多个输入数据以时间顺序生成内插数据; 第一模拟数字转换器，被配置为将内插数据的数据点处的第一内插数据转换为第一数字数据; 以及第二模拟数字转换器，其被配置为将变化点处的第二内插数据转换成所述内插数据的第二数字数据，所述第二模拟数字转换器的第二数量的量化比特小于所述第一模拟数字转换器的第一数量的量化比特 数字转换器。
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6.发明授权High-speed analog-digital converter having a signal folding structure improved by reducing the number of elementary cells 有权具有信号折叠结构的高速模拟数字转换器通过减少基本单元的数量而得到改善公开(公告)号：US08184032B2
公开(公告)日：2012-05-22
申请号：US12936312
申请日：2009-03-26
申请人： Sandrine Bruel , François Bore
发明人： Sandrine Bruel , François Bore
IPC分类号： H03M1/34
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/203
摘要： The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.
摘要翻译： 本发明涉及使用由差分电路（交叉差分对）和负载（共源共栅晶体管）组成的所谓的折叠差分放大器结构的高分辨率模数转换器。 根据本发明的折叠结构包括在希望产生在要转换的电压的有用范围内的两个周期折叠的四个曲线的情况下，四个折叠块（每个曲线一个）。 第一个包括7个差分电路和8个负载，终端负载不连接到块的输出。 其他块包括6个差分电路和8个负载，每个块的最后一个负载不链接到该块的输出。 在现有结构方面，在批量，消费和运行速度方面实现了收益。
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7.发明授权Signal processing apparatus generating a signal having a fequency corresponding to the sum of frequencies of input signals for displacement detection 失效信号处理装置生成具有与用于位移检测的输入信号的频率之和相对应的频率的信号
公开(公告)号：US5528227A
公开(公告)日：1996-06-18
申请号：US100217
申请日：1993-08-02
申请人： Tadashi Eguchi
发明人： Tadashi Eguchi
CPC分类号： H03M1/203 , G01D5/24404 , H03M1/303
摘要： A signal processing method includes the steps of inputting first to N-th 2-phase sinusoidal wave signals, where N is a natural number (N.ltoreq.2) and an m-th 2-phase sinusoidal wave signal has an m-th frequency where m is a natural number and satisfies a relation of 1.ltoreq.m.ltoreq.N, and processing the first to N-th 2-phase sinusoidal signals by product summation or product differentiation of the first to N-th 2-phase sinusoidal wave signals to produce at least one signal having a frequency equal to a sum of the frequencies of the first to N-th 2-phase sinusoidal wave signals.
摘要翻译： 信号处理方法包括以下步骤：输入第一到第N相的正弦波信号，其中N是自然数（N <2），第m个2相正弦波信号具有第m个 频率，其中m是自然数，并且满足1≤n≤N的关系，并且通过第一至第N-2的乘积求和或乘积微分来处理第一至第N二阶正弦信号， 产生相位正弦波信号以产生具有等于第一至第N相正弦波信号的频率之和的频率的至少一个信号。
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公开(公告)号：US4200863A
公开(公告)日：1980-04-29
申请号：US968590
申请日：1978-12-11
申请人： David A. Hodges , Paul R. Gray , James L. McCreary
发明人： David A. Hodges , Paul R. Gray , James L. McCreary
摘要： An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed. Resolution of the coder/decoder is increased by providing a reference voltage generator capable of supplying stepped increments of the reference voltage to the capacitor array during the comparison process.
摘要翻译： 二进制加权电容器阵列，具有与二进制加权电容器中最少的电容值相当的电容值的附加电容器，电压比较器，用于将电容器与某些预定电压电平互连的开关和比较器，以及排序电路 。 所有电容器的一侧连接到比较器上的一个输入端子，而另一侧则向其施加要量化的信号。 开关顺序将参考电压的分割部分与要量化的信号相结合，以便呈现给比较器的输入，从而提供连接到排序电路的串行数字输出。 以这种方式，由定序电路进行模拟和数字信号之间的线性转换。 还公开了数字和模拟信号呈现之间的非线性转换器。 编码器/解码器的分辨率通过提供一个参考电压发生器来增加，该参考电压发生器能够在比较过程期间向电容器阵列提供参考电压的阶梯式增量。
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公开(公告)号：US20240223205A1
公开(公告)日：2024-07-04
申请号：US18354370
申请日：2023-07-18
CPC分类号： H03M1/203 , H03M1/182 , H03M7/3004
摘要： Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.
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公开(公告)号：US20160315629A1
公开(公告)日：2016-10-27
申请号：US14871373
申请日：2015-09-30
CPC分类号： H03M1/0609 , H03M1/203 , H03M1/361
摘要： In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
摘要翻译： 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。
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