公开(公告)号：US4818996A

公开(公告)日：1989-04-04

申请号：US97846

申请日：1987-09-16

Applicant: Shigenobu Kimura

Inventor： Shigenobu Kimura

IPC: H03M1/70 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/70

Abstract: A digital-to-analog converting circuit increases an absolute value of inputted digital data by a bit shift operation when minute digital data are inputted thereto. The shifted digital data are converted into an analog signal, and thereafter, such analog signal is attenuated in accordance with a shift value of the bit shift operation. The bit shift operation and the attenuation operation are performed when the value of the inputted digital data are smaller than a predetermined value for a predetermined time or more. Thus, a conversion accuracy of the minute digital data is raised, and a distortion generation depending on a frequently switching of the bit shift is avoided.

Abstract translation: 数字 - 模拟转换电路当输入微小的数字数据时，通过位移操作增加输入的数字数据的绝对值。 移位的数字数据被转换为模拟信号，此后，这种模拟信号根据位移操作的移位值被衰减。 当输入的数字数据的值小于预定值达预定时间或更长时，执行位移操作和衰减操作。 因此，微小数字数据的转换精度提高，并且避免了根据位移的频繁切换产生的失真。

公开(公告)号：US4692738A

公开(公告)日：1987-09-08

申请号：US711382

申请日：1985-03-13

Applicant: Seigo Suzuki

Inventor： Seigo Suzuki

IPC: H03M1/10 ,  G06F3/05 ,  G06G7/26 ,  G06J1/00 ,  H03M1/00 ,  G06G7/12 ,  H03K13/02

CPC classification number: G06J1/00 ,  G06F3/05 ,  H03M1/02 ,  H03M1/165

Abstract: An analog signal is input to an A/D converting section. This A/D converting section has a D/A converter therein. The A/D converting section converts the input analog signal to a digital signal. A digital signal processing circuit receives an output signal from the A/D converting section and performs a predetermined process to this signal. A D/A converting section receives and converts an output signal of the digital signal processing circuit to an analog signal. This D/A converting section has a D/A converter with the same circuit arrangement as the D/A converter in the A/D converting section circuit and is constituted by the same circuit pattern. Therefore, the converting functions of the A/D converting section and of the D/A converting section are inverse functions of each other, so that error or distortion, which is caused in the A/D converting section, is automatically corrected when the digital signal is reconverted to the analog signal in the D/A converting section.

Abstract translation: 模拟信号被输入到A / D转换部分。 该A / D转换部分具有D / A转换器。 A / D转换部分将输入的模拟信号转换为数字信号。 数字信号处理电路接收来自A / D变换部的输出信号，对该信号进行规定的处理。 D / A转换部分将数字信号处理电路的输出信号转换为模拟信号。 该D / A转换部分具有与A / D转换部分电路中的D / A转换器相同的电路布置的D / A转换器，并且由相同的电路图形构成。 因此，A / D转换部分和D / A转换部分的转换功能是彼此的反向功能，因此当数字（A / D转换部分）数字化时，A / D转换部分引起的错误或失真被自动校正 信号被转换为D / A转换部分中的模拟信号。

公开(公告)号：US4677581A

公开(公告)日：1987-06-30

申请号：US739263

申请日：1985-05-30

Applicant: Jacob H. Malka ,  Philip J. Thurakal

Inventor： Jacob H. Malka ,  Philip J. Thurakal

IPC: G01R31/28 ,  G01R31/3167 ,  G06F3/05 ,  G06J1/00 ,  H03K13/02

CPC classification number: G01R31/2841 ,  G01R31/3167 ,  G06F3/05 ,  G06J1/00

Abstract: Analog input/output apparatus includes a plurality of digital to analog converters (18, 20, 22, 24, 26) and a plurality of interfacing means (4, 6, 8, 10, 12, 14, 16) for interfacing the converters with a central processing unit (2). A plurality of current and voltage sources (28, 30, 32, 34, 36, 38, 40, 42) are connected to the converters for providing a plurality of voltage and current stimuli signals and monitor signals. A signal measurement channel (44, 46, 48, 52) is responsive to the monitor signals and is controlled by the interfacing means (4-16), and multiplexers (44, 46) are wrapped around the measurement channel to provide a self-calibration channel (50). The central processing unit is responsive to the self-calibration channel output for determining the correction to be applied to the stimuli signals.

Abstract translation: 模拟输入/输出设备包括多个数模转换器（18,20,22,24,26）和多个接口装置（4,6,8,10,12,14,16），用于将转换器与 中央处理单元（2）。 多个电流和电压源（28,30,32,34,36,38,40,42）连接到转换器，用于提供多个电压和电流刺激信号以及监视信号。 信号测量通道（44,46,48,52）响应于监视器信号并由接口装置（4-16）控制，多路复用器（44,46）被缠绕在测量通道周围， 校准通道（50）。 中央处理单元响应于自校准通道输出以确定要应用于刺激信号的校正。

公开(公告)号：US4673916A

公开(公告)日：1987-06-16

申请号：US475404

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

IPC: H03M1/12 ,  G10L19/00 ,  G11B20/10 ,  H03M1/00 ,  H04B14/04 ,  H04M1/65 ,  H03K13/02

CPC classification number: H04M1/6505 ,  G11B20/10527 ,  H03M1/74

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum indicating the sampling interval of the digital samples are written into a read-write memory (M2). The digital samples and the associated sampling datum are read out of the memory into first and second digital-to-analog converters (DAC1, DAC2), respectively. The output of the first digital-to-analog converter is applied to a variable frequency low-pass filter (5) to remove the components having frequencies higher than a presettable frequency limit value which is variable as a function of the output of the second digital-to-analog converter so that the cut-off frequency is lower than one-half the sampling frequency to eliminate quantum noise.

Abstract translation: 在数据压缩系统中，包括一系列数字样本的数字信号和指示数字样本的采样间隔的采样数据被写入读写存储器（M2）。 数字采样和相关采样数据分别从存储器读出到第一和第二数模转换器（DAC1，DAC2）。 第一数模转换器的输出被施加到可变频率低通滤波器（5），以去除具有高于可预设频率极限值的频率的分量，该频率限制值作为第二数字 - 模拟转换器 模拟转换器，使得截止频率低于采样频率的一半，以消除量子噪声。

公开(公告)号：US4665381A

公开(公告)日：1987-05-12

申请号：US601247

申请日：1984-04-17

Applicant: Eiji Masuda ,  Yasuhiko Fujita

Inventor： Eiji Masuda ,  Yasuhiko Fujita

IPC: H03M1/76 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/808 ,  H03M1/365

Abstract: In a D/A converter, a reference voltage is divided into a plurality of divided voltages by a plurality of resistors connected in series. The divided voltages are respectively selected by switches which are turned on according to the contents of a digital input. With the use of an expanding bit or bits, a plurality of the switches are simultaneously turned on.

Abstract translation: 在D / A转换器中，通过串联连接的多个电阻将参考电压分成多个分压。 根据数字输入的内容，开关分别选择分压。 通过使用扩展位或位，多个开关同时导通。

公开(公告)号：US4638302A

公开(公告)日：1987-01-20

申请号：US766136

申请日：1985-08-15

Applicant: Eddy So ,  William J. M. Moore

Inventor： Eddy So ,  William J. M. Moore

IPC: H03M1/00 ,  H03K13/02

CPC classification number: H03M1/68

Abstract: A converter for converting a series of digital input bits to an analog output employs a direct current comparator having a magnetic core and primary and secondary ratio windings coupled with the core. The primary winding is divided into two sections. A first group of the more significant input bits varies the number of turns of the first primary section which is traversed by a first direct current. A second group of less significant input bits varies the number of turns of the second primary section traversed by a second direct current. A direct current is also passed through the secondary winding, this secondary current being varied proportionally with the number of turns of the first primary section traversed by the first primary current. Modulation-detection windings arranged inside the core (which also acts as a magnetic shield) detect any net ampere-turns unbalance of the primary and secondary currents in the ratio windings. Detection of such an unbalance further varies the secondary current to tend to bring the unbalance to zero. The analog output is proportional to the secondary current. The splitting of the primary winding into two sections enables the converter to handle a larger number of bits, e.g. 20, than would be possible with a prior art type of primary winding, without the number of turns becoming unmanageably large.

Abstract translation: 用于将一系列数字输入位转换为模拟输出的A转换器采用直流电流比较器，其具有与磁芯耦合的磁芯和初级和次级绕组绕组。 初级绕组分为两部分。 第一组更重要的输入位改变由第一直流电流穿过的第一主要部分的匝数。 第二组较不重要的输入位改变由第二直流电流穿过的第二主要部分的匝数。 直流电流也通过次级绕组，该次级电流与第一初级电流横穿的第一初级绕组的匝数成比例变化。 布置在芯体内部的调制检测绕组（也用作磁屏蔽）可以检测绕组比率中的一次侧和次级电流的任何净安培回路不平衡。 这种不平衡的检测进一步改变次级电流，以使不平衡趋于零。 模拟输出与次级电流成正比。 将初级绕组分成两部分使得转换器能够处理更大数量的位，例如， 20，与现有技术类型的初级绕组相比，没有转弯变得难以控制的程度。

公开(公告)号：US4633223A

公开(公告)日：1986-12-30

申请号：US738265

申请日：1985-05-28

Applicant: Daniel Senderowicz

Inventor： Daniel Senderowicz

IPC: H03F3/00 ,  H03F3/45 ,  H03H19/00 ,  H03K13/02

CPC classification number: H03F3/45479 ,  H03F3/005 ,  H03H19/004 ,  H03F2200/372

Abstract: An integrated circuit employing a differential integrator and switched capacitor network to provide auto-zeroing. The differential integrator utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier provides voltage division of differential reference signals which determine the amount of DC offset. The amplifier then integrates the reference signals to a predetermined time constant, wherein the average voltage of the output of the integrator is used to provide auto-correction of the DC offset. A second switched capacitor voltage divider network and a second differential integrator cascaded to the first circuit provides a second time constant for fine-tuning the auto-correction signal.

Abstract translation: 采用差分积分器和开关电容网络的集成电路提供自动归零。 差分积分器利用其输入和输出之间的反馈电路。 耦合到放大器的输入的开关电容器网络提供了确定DC偏移量的差分参考信号的分压。 然后，放大器将参考信号积分到预定时间常数，其中积分器的输出的平均电压用于提供DC偏移的自动校正。 级联到第一电路的第二开关电容器分压器网络和第二差分积分器提供用于微调自动校正信号的第二时间常数。

公开(公告)号：US4631518A

公开(公告)日：1986-12-23

申请号：US653617

申请日：1984-09-24

Applicant: George J. Caspell

Inventor： George J. Caspell

IPC: H03M1/66 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/187

Abstract: A device for controlling the output voltage range of a digital-to-analog (D/A) converter of the type wherein the converter output voltage range is proportional to the magnitude of an applied bias current. The device comprises means to sample and store a selected converter output voltage, means to produce a variable current of magnitude proportional to the stored converter output voltage, and a source of constant current. The constant current and the variable current are summed and applied to the converter as the bias current. The converter output voltage range is dependent on the variable portion of the applied bias current which is in turn dependent on the stored, selected converter output voltage.

Abstract translation: 一种用于控制这种类型的数/模（D / A）转换器的输出电压范围的装置，其中转换器输出电压范围与施加的偏置电流的幅度成比例。 该装置包括对所选择的转换器输出电压进行采样和存储的装置，用于产生与所存储的转换器输出电压成比例的可变电流大小的量值和恒定电流源的装置。 将恒定电流和可变电流相加并作为偏置电流施加到转换器。 转换器输出电压范围取决于所施加的偏置电流的可变部分，其依赖于所存储的所选转换器输出电压。

公开(公告)号：US4623874A

公开(公告)日：1986-11-18

申请号：US667662

申请日：1984-11-02

Applicant: Donald E. Thoma

Inventor： Donald E. Thoma

IPC: G06F5/01 ,  H03K13/02

CPC classification number: G06F5/01

Abstract: A bidirectional word length converter for use in transferring data between a first data processing unit and second data processing unit each using a word format of a different length. The converter includes a buffer connected between the first and second units and a converter control. The converter control is adapted to accept a plurality of mode signals from the first unit to control the transfer of data in a first length word format from the first unit to the second unit in a second length word format. The converter control is further adapted to accept an alternative plurality of mode signals to transfer data from the second unit to the first unit in a similar manner.

Abstract translation: 一种用于在第一数据处理单元和第二数据处理单元之间传送数据的双向字长转换器，每个使用不同长度的字格式。 该转换器包括连接在第一和第二单元之间的缓冲器和转换器控制器。 转换器控制适于接受来自第一单元的多个模式信号，以第二长度字格式控制从第一单元到第二单元的第一长度字格式的数据传送。 转换器控制还适于接受可选的多个模式信号，以类似的方式将数据从第二单元传送到第一单元。

公开(公告)号：US4620178A

公开(公告)日：1986-10-28

申请号：US580690

申请日：1984-02-16

Applicant: Kazufumi Naito

Inventor： Kazufumi Naito

IPC: G01G23/37 ,  H03M1/00 ,  H03K13/02

CPC classification number: G01G23/3707 ,  H03M1/1047

Abstract: A double-integrating A/D converter in which an integrator output voltage, produced by integrating an analog signal input thereto, is reverse-integrated in accordance with a reference voltage having a polarity opposite to that of the analog signal. The time required for the reverse integration is measured in the form of a pulse count by means of a counter. A microcomputer for controlling the counter and a switch which selects the input to the integrator are provided with a software timer function so that the integrating interval of the analog input signal is set at will. The microcomputer also is capable of calculating a digital value, which corresponds to the analog signal, from a count recorded in the counter and from an overflow value indicated by an overflow signal generated by the counter. The signal converted by the A/D converter is capable of being applied to the weighing section of an electronic weigher.

Abstract translation: 一种双积分A / D转换器，其中通过对输入到其上的模拟信号进行积分而产生的积分器输出电压根据与模拟信号的极性相反的参考电压被反向积分。 通过计数器以脉冲计数的形式测量反向积分所需的时间。 用于控制计数器的微计算机和选择对积分器的输入的开关具有软件定时器功能，使得模拟输入信号的积分间隔随意设定。 微计算机还能够从记录在计数器中的计数和由计数器产生的溢出信号所指示的溢出值计算对应于模拟信号的数字值。 由A / D转换器转换的信号能够应用于电子称重器的称重部分。