公开(公告)号：US09157884B2

公开(公告)日：2015-10-13

申请号：US13218113

申请日：2011-08-25

Applicant: Masayoshi Seike ,  Nobuyasu Hori ,  Seigo Suzuki ,  Shigeki Iwanaga ,  Hiroya Kirimura

Inventor： Masayoshi Seike ,  Nobuyasu Hori ,  Seigo Suzuki ,  Shigeki Iwanaga ,  Hiroya Kirimura

IPC: G01N27/26 ,  G01N27/327 ,  G01N27/74

CPC classification number: G01N27/3278 ,  G01N27/745

Abstract: In order to provide a method of electrochemically detecting a target substance, a method of electrochemically detecting an analyte, and a detection set which have a theoretical advantage in the measurement sensitivity obtained by a conventional electrochemical detection method using a working electrode with a trapping substance immobilized, can reuse the working electrode, and can detect an analyte regardless of the size thereof, there is provided a method including: attracting the target substance containing a labeling substance in a liquid sample to a working electrode in which a trapping substance for trapping the target substance containing a labeling substance is not present; and electrochemically detecting the target substance containing a labeling substance.

Abstract translation: 为了提供电化学检测目标物质的方法，电化学检测分析物的方法和检测组，其具有通过常规电化学检测方法获得的测量灵敏度的理论上的优势，所述电化学检测方法使用固定有捕获物质的工作电极 可以重复利用工作电极，并且可以检测分析物而不考虑其大小，提供了一种方法，包括：将含有液体样品中的标记物质的目标物质吸引到用于捕获靶的捕获物质的工作电极 不含标签物质的物质不存在; 并电化学检测含有标记物质的目标物质。

公开(公告)号：US5973401A

公开(公告)日：1999-10-26

申请号：US892203

申请日：1997-07-14

Applicant: Seigo Suzuki

Inventor： Seigo Suzuki

IPC: G02B6/42 ,  G02B6/43 ,  H01L23/34 ,  H01L23/48

CPC classification number: G02B6/43 ,  G02B6/4201 ,  H01L23/34 ,  H01L23/48 ,  H01L2924/0002

Abstract: Disclosed are semiconductor devices employing chips comprising highly integrating semiconductor elements, and having various means for controlling temperature increase of the chips. These means comprise three approaches: means for controlling heat generation by adjusting clock frequencies to be supplied to the chips respectively; means for suppressing heat generation by suitably arranging the wiring construction of the chip substrate; and means for suppressing heat generation of sub-chips by a prarallel process such as optical communication between the sub-chips.

Abstract translation: 公开了采用包含高度集成半导体元件的芯片的半导体器件，并且具有用于控制芯片温度升高的各种装置。 这些手段包括三种方法：分别通过调整提供给芯片的时钟频率来控制发热的装置; 用于通过适当地布置芯片基板的布线结构来抑制发热的装置; 以及用于通过诸如子芯片之间的光通信的并行处理来抑制子芯片的发热的装置。

公开(公告)号：US4945518A

公开(公告)日：1990-07-31

申请号：US363276

申请日：1989-06-08

Applicant: Kunio Muramatsu ,  Seigo Suzuki

Inventor： Kunio Muramatsu ,  Seigo Suzuki

IPC: G06F5/06 ,  G06F5/12 ,  G06F5/16 ,  G06T1/60 ,  G09G5/00 ,  G11C7/00

CPC classification number: G06F5/16 ,  G11C7/00

Abstract: A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (D.sub.in) into the cell (1) at a predetermined rate and resetting the write address of the cell (1) at a predetermined period, a read circuit (5, 6, 7) for reading data (D.sub.out) from cell (1) at a rate different from the write rate and resetting the read address of the cell (1) at the predetermined period, the first shift circuit (8) for shifting reset timing of the write address, and the second shift circuit (9) for shifting reset timing of the read address, the first and second shift circuits enabling respective setting quantities at the same value. This memory can shift both the write address reset timing and the read address reset timing while keeping both in the same condition.

公开(公告)号：US4802136A

公开(公告)日：1989-01-31

申请号：US188672

申请日：1988-04-29

Applicant: Sigeru Nose ,  Seigo Suzuki

Inventor： Sigeru Nose ,  Seigo Suzuki

IPC: H03K5/135 ,  G11C19/00 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C19/00

Abstract: A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.

Abstract translation: 数据延迟/存储电路包括由级联连接的时钟反相器形成的时钟控制数据锁存电路。 数据延迟/存储电路还包括用于向时钟反相器提供时钟信号的时钟发生器。 这些时钟信号具有单独的时钟相位，并且被顺序地产生，使得数据锁存电路的最后级的时钟相位在其初始阶段之前。

公开(公告)号：US4509188A

公开(公告)日：1985-04-02

申请号：US504747

申请日：1983-06-16

Applicant: Seigo Suzuki

Inventor： Seigo Suzuki

IPC: G10L19/06 ,  G06G7/16 ,  G10L13/00 ,  G10L13/04 ,  G10L19/00 ,  G10L1/00

CPC classification number: G10L13/047

Abstract: A signal synthesizer apparatus having a parameter dependent multiplier which includes charge-coupled devices. The multiplier has a gating input to store a charge corresponding to an input signal applied thereto; a transmission circuit for selectively transferring portions of the stored input charge, the selectivity of the transmission circuit being dependent on the prescribed parameter; and an output for receiving and combining all of the charges transferred from the transmission circuit. The transmission circuit comprises a first circuit for selectively dividing the charge corresponding to the input signal into given fragments and for transferring the divided charge, and a second circuit for determining the selectivity of the dividing of the charge according to the prescribed parameter. The rate of the dividing of charge corresponds to the multiplicative coefficient of the multiplier.

公开(公告)号：US4394730A

公开(公告)日：1983-07-19

申请号：US197566

申请日：1980-10-16

Applicant: Seigo Suzuki ,  Seiji Eguchi

Inventor： Seigo Suzuki ,  Seiji Eguchi

IPC: G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

CPC classification number: G06F15/167 ,  G06F9/4812 ,  G06F9/4856

Abstract: A multi-processor system having a priority control wherein jobs are transferred between processors in a multi-processor system when a new job is accepted by the system. The processors are arranged in a predetermined priority sequence and in response to an interrupt command, the system always directs a transferred job to which priority processor whose currently executing job is transferred to a lower priority processor. Jobs are transferred by shifting linkage information from one processor to the other through a common control memory in accordance with a job transfer program at each processor. When the interrupt cycle is completed, transferred jobs are returned to the processor at which they were being processed prior to the interrupt.

Abstract translation: 一种具有优先级控制的多处理器系统，其中当系统接受新作业时，作业在多处理器系统中的处理器之间传送。 处理器以预定的优先级顺序排列，并且响应于中断命令，系统总是将其当前执行的作业被传送到的优先处理器的传送作业定向到较低优先级的处理器。 通过根据每个处理器上的作业传送程序，通过公共控制存储器将链接信息从一个处理器移动到另一个处理器来传送作业。 当中断周期完成后，传送的作业将在中断之前返回到处理器。

公开(公告)号：US4292941A

公开(公告)日：1981-10-06

申请号：US176292

申请日：1980-08-08

Applicant: Seigo Suzuki

Inventor： Seigo Suzuki

IPC: F02P5/15 ,  F02P7/067 ,  F02P5/04

CPC classification number: F02P7/067

Abstract: There are provided a counter, a memory device which stores a combustion delay information, that is an information regarding the time delay between ignition initiation and combustion, and a processor. In response to a clock pulse the counter measures the interval between adjacent combustion initiation points and produces a count information corresponding to the combustion interval. The combustion delay information is read out of the memory device by the count information. The processor produces an ignition time information in response to the count information and the combustion delay information. The ignition time information contains an information corresponding to the difference between the combustion initiation points and the combustion delay time, and is used to generate a succeeding ignition initiation time.

Abstract translation: 设置有计数器，存储燃烧延迟信息的存储装置，即燃烧延迟信息，其是关于点火开始和燃烧之间的时间延迟的信息以及处理器。 响应于时钟脉冲，计数器测量相邻燃烧起始点之间的间隔，并产生对应于燃烧间隔的计数信息。 通过计数信息从存储装置读出燃烧延迟信息。 处理器响应于计数信息和燃烧延迟信息产生点火时间信息。 点火时间信息包含对应于燃烧起始点和燃烧延迟时间之间的差异的信息，并且用于产生随后的点火开始时间。

公开(公告)号：US4163291A

公开(公告)日：1979-07-31

申请号：US732965

申请日：1976-10-15

Applicant: Seigo Suzuki ,  Yoshiaki Moriya

Inventor： Seigo Suzuki ,  Yoshiaki Moriya

IPC: G06F5/08 ,  G11C19/28 ,  G11C7/00 ,  G11C19/00

CPC classification number: G06F5/08 ,  G11C19/28

Abstract: In transmitting data between a plurality of sequentially connected FIFO type memory elements by controlling a binary coded signal a circuit element is provided in a manner to correspond to each memory element, so as to indicate a data storage state. A circuit element comprises flip-flop constructed of two NOR circuits, the input of each NOR circuit being connected to an input control line or an output control line, and inverters each of which is connected to the output of the NOR circuit. The provision of such circuit element permits an automatic data transmission control according to a data storage state in a specified memory element and a data storage state in the next stage memory element.

Abstract translation: 在通过控制二进制编码信号在多个顺序连接的FIFO型存储器元件之间传送数据时，以与每个存储器元件对应的方式提供电路元件，以指示数据存储状态。 电路元件包括由两个NOR电路构成的触发器，每个NOR电路的输入连接到输入控制线或输出控制线，以及各自连接到NOR电路的输出的反相器。 提供这种电路元件允许根据指定存储元件中的数据存储状态和下一级存储元件中的数据存储状态的自动数据传输控制。

公开(公告)号：US4138732A

公开(公告)日：1979-02-06

申请号：US735961

申请日：1976-10-27

Applicant: Seigo Suzuki ,  Keiji Uemori

Inventor： Seigo Suzuki ,  Keiji Uemori

IPC: G06F13/38 ,  G06F5/10 ,  G06F7/78 ,  G06F13/00 ,  G11C19/00

CPC classification number: G06F7/785 ,  G06F5/10

Abstract: A data transfer control system for controlling data transfer between a processor and an input/output device comprises a multi-layer stack for temporarily storing transfer data, such as a first-in first-out stack or a last-in first-out stack; first and second up/down counters having a preset function and permitting any designated address at the stack to be varied; and first and second pointer registers for storing any initially designated address data which is stored in the counter. The first counter permits a direction of a count operation to be determined by the processor and the first point register has an initially designated address data stored therein by the processor. The second counter permits a direction of a count operation to be determined by the input/output device and the second point register has an initially designated address data stored therein by the input/output device. The direction of a data flow at the stack is varied dependent upon the direction in which the first and second counters effect count operations.

Abstract translation: 用于控制处理器和输入/输出设备之间的数据传输的数据传输控制系统包括用于临时存储传输数据的多层堆栈，诸如先进先出堆叠或先进先出堆栈; 具有预设功能的第一和第二上/下计数器，并允许堆栈中的任何指定地址变化; 以及用于存储存储在计数器中的任何最初指定的地址数据的第一和第二指针寄存器。 第一计数器允许由处理器确定计数操作的方向，并且第一点寄存器具有由处理器存储在其中的初始指定的地址数据。 第二计数器允许由输入/输出设备确定计数操作的方向，并且第二点寄存器具有由输入/输出设备存储在其中的初始指定的地址数据。 堆栈上的数据流的方向取决于第一和第二计数器影响计数操作的方向。

公开(公告)号：US4115868A

公开(公告)日：1978-09-19

申请号：US732703

申请日：1976-10-15

Applicant: Seigo Suzuki ,  Seiji Eguchi ,  Yoshiaki Moriya

Inventor： Seigo Suzuki ,  Seiji Eguchi ,  Yoshiaki Moriya

IPC: G06F13/38 ,  G06F5/06 ,  G06F13/00

CPC classification number: G06F5/06

Abstract: An information transferring apparatus disposed between first and second information processing units comprises a first-in first-out stack, a first information line for transferring information from the first information processing unit to the first-in first-out stack, a second information line for transferring information from the first-in first-out stack to the second information processing unit, a third information line for transferring information from the second information processing unit to the first-in first-out stack, a fourth information line for transferring information from the first-in first-out stack to the first information processing unit, switching circuits for selectively deactivating the first to fourth information lines, and a command register for applying first and second control signals to the switching circuits, wherein the switching circuits operate responsive to the first control signal from the command register to deactivate the third and fourth information lines while holding active the first and second information lines, and operate responsive to the second control signal from the command register to deactivate the first and second information lines while holding active the third and fourth information lines. The command register may be replaced and its functions performed by either manual control or an external circuit.

Abstract translation: 设置在第一和第二信息处理单元之间的信息传送装置包括先进先出堆叠，用于将信息从第一信息处理单元传送到先进先出堆栈的第一信息行，用于 将信息从先进先出堆栈传送到第二信息处理单元，用于将信息从第二信息处理单元传送到先进先出堆栈的第三信息线，用于从第一信息处理单元传送信息的第四信息行 第一信息处理单元的先进先出堆叠，用于选择性地去激活第一至第四信息线的开关电路和用于将第一和第二控制信号施加到开关电路的命令寄存器，其中开关电路响应于 来自命令寄存器的第一个控制信号，用于禁用第三和第四个信息 同时保持活动的第一和第二信息行，并响应于来自命令寄存器的第二控制信号而操作，以在保持活动第三和第四信息行的同时停用第一和第二信息行。 命令寄存器可以被替换，其功能由手动控制或外部电路执行。