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    A/D converter circuit and semiconductor integrated circuit
    4.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权
    A / D转换电路和半导体集成电路

    公开(公告)号：US09124284B2

    公开(公告)日：2015-09-01

    申请号：US14579049

    申请日：2014-12-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/00 ,  H03M1/44

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    Abstract translation: 一种具有简单设计并能够防止表面积增加和其他问题的模数转换器电路。 用于将模拟输入信号转换为数字量的模数转换器电路包括将模拟输入信号转换成预校正数字值的模数转换器单元，以及对预连接进行数字校正的校正单元 从模数转换器单元输出的数字值。 校正单元包括加权系数乘法器单元，其输出通过将从每个比特提供的加权系数乘以从A / D转换器单元输出的预校正数字值的每一位并将其相加得到的校正后数字值，以及 加权系数搜索单元，其搜索加权系数，以便最小化基于校正后数字值产生的误差信号和校正后数字值的近似值。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09100034B2

    公开(公告)日：2015-08-04

    申请号：US14203052

    申请日：2014-03-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura

    IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46

    CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

    Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。

    Electronic system and operating method thereof
    6.
    发明授权
    Electronic system and operating method thereof 有权
    电子系统及其操作方法

    公开(公告)号：US09054723B2

    公开(公告)日：2015-06-09

    申请号：US14274813

    申请日：2014-05-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura

    IPC: H03M1/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/66

    CPC classification number: H03M1/1033 ,  H03M1/002 ,  H03M1/1052 ,  H03M1/12 ,  H03M1/201 ,  H03M1/44 ,  H03M1/46 ,  H03M1/66 ,  H03M1/745

    Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

    Abstract translation: 为了补偿包括DA转换单元和AD转换单元的电子系统中的AD转换单元的非线性和DA转换单元的非线性，电子系统包括A / D转换单元，D / A 转换单元，AD转换补偿单元，DA转换补偿单元和校准单元。 在校准操作期间，校准单元设定AD转换补偿单元的工作特性和DA转换补偿单元的工作特性。 在校准操作期间设定的AD转换补偿单元的工作特性补偿A / D转换单元的AD转换的非线性。 在校准操作期间设置的DA转换补偿单元的工作特性补偿D / A转换单元的DA转换的非线性。

    SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD THEREFOR
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD THEREFOR 有权
    半导体器件及其调整方法

    公开(公告)号：US20130102264A1

    公开(公告)日：2013-04-25

    申请号：US13657765

    申请日：2012-10-22

    Applicant: Renesas Electronics Corporation

    Inventor： Hideo NAKANE ,  Keisuke Kimura ,  Takaya Yamamoto ,  Tatsuji Matsuura ,  Ryuichi Ujiie

    IPC: G06F3/033

    CPC classification number: H03M1/1004 ,  H03M1/1009 ,  H04B1/1027

    Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.

    Abstract translation: 提供了能够在接收操作期间执行背景校准而不会不利地影响接收特性的半导体器件。 在接收操作期间，半导体器件检测在增益改变或接收信道改变时发生无效接收信号的定时，并在检测到的定时执行背景校准。 在这种情况下，由于接收信号无效，进行校准不会进一步降低接收的实质准确性。 此外，只要在随机定时执行背景校准，就不会产生当以固定间隔执行背景校准时将产生的不必要的信号分量。

    A/D converter circuit and semiconductor integrated circuit
    10.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权

    公开(公告)号：US09362932B2

    公开(公告)日：2016-06-07

    申请号：US14817645

    申请日：2015-08-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

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