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    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08686885B2

    公开(公告)日：2014-04-01

    申请号：US13744284

    申请日：2013-01-17

    Applicant: Renesas Electronics Corporation

    Inventor： Tatsuji Matsuura ,  Hideo Nakane ,  Masumi Kasahara ,  Ryuichi Ujiie ,  Keisuke Kimura ,  Oshima Takashi

    IPC: H03M1/10

    CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/1071 ,  H03M1/123

    Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.

    Abstract translation: 具有用于通过数字校正处理将模拟输入信号转换成数字信号的A / D转换器的半导体集成电路器件面积减小。 半导体集成电路器件具有第一A / D转换器和第二A / D转换器。 在第一模式中，第一测试信号被输入到第一和第二A / D转换器，并且计算第一A / D转换器的第一校正系数和第二A / D转换器的第二校正系数。 在第二模式中，第一A / D转换器通过对第一模拟信号进行第一数字校正处理而将第一模拟信号转换为第一数字信号，并且第二A / D转换器将第二模拟信号转换为第二数字信号 通过对第二模拟信号进行第二数字校正处理。

    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus
    3.
    发明授权
    Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus 有权
    具有与增益相关的抖动和通信装置的模数转换器的半导体器件

    公开(公告)号：US09007245B2

    公开(公告)日：2015-04-14

    申请号：US14445682

    申请日：2014-07-29

    Applicant: Renesas Electronics Corporation

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

    IPC: H03M1/20 ,  H03M3/00

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    Semiconductor device and adjustment method therefor
    4.
    发明授权
    Semiconductor device and adjustment method therefor 有权
    半导体器件及其调整方法

    公开(公告)号：US08886141B2

    公开(公告)日：2014-11-11

    申请号：US13657765

    申请日：2012-10-22

    Applicant: RENESAS Electronics Corporation

    Inventor： Hideo Nakane ,  Keisuke Kimura ,  Takaya Yamamoto ,  Tatsuji Matsuura ,  Ryuichi Ujiie

    IPC: H04B17/02 ,  H03M1/10 ,  H04B1/10

    CPC classification number: H03M1/1004 ,  H03M1/1009 ,  H04B1/1027

    Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.

    Abstract translation: 提供了能够在接收操作期间执行背景校准而不会不利地影响接收特性的半导体器件。 在接收操作期间，半导体器件检测在增益改变或接收信道改变时发生无效接收信号的定时，并在检测到的定时执行背景校准。 在这种情况下，由于接收信号无效，进行校准不会进一步降低接收的实质准确性。 此外，只要在随机定时执行背景校准，就不会产生当以固定间隔执行背景校准时将产生的不必要的信号分量。

    Semiconductor device having analog-to-digital converter with gain-dependent dithering and communication apparatus
    6.
    发明授权
    Semiconductor device having analog-to-digital converter with gain-dependent dithering and communication apparatus 有权
    具有与增益相关的抖动和通信装置的模数转换器的半导体器件

    公开(公告)号：US08823565B2

    公开(公告)日：2014-09-02

    申请号：US13940819

    申请日：2013-07-12

    Applicant: Renesas Electronics Corporation

    Inventor： Keisuke Kimura ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/20

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    Semiconductor Device Having Analog-To-Digital Converter With Gain-Dependent Dithering And Communication Apparatus
    7.
    发明申请
    Semiconductor Device Having Analog-To-Digital Converter With Gain-Dependent Dithering And Communication Apparatus 有权
    具有增益依赖抖动和通信设备的模数转换器的半导体器件

    公开(公告)号：US20140333461A1

    公开(公告)日：2014-11-13

    申请号：US14445682

    申请日：2014-07-29

    Applicant: Renesas Electronics Corporation

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

    IPC: H03M3/00 ,  H03M1/20

    CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

    Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

    Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09100034B2

    公开(公告)日：2015-08-04

    申请号：US14203052

    申请日：2014-03-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Keisuke Kimura

    IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46

    CPC classification number: H03M1/1245 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/0639 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/56

    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

    Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近，数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正， 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。

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