公开(公告)号：US20170237268A1

公开(公告)日：2017-08-17

申请号：US15169981

申请日：2016-06-01

Applicant: Analog Devices Global

Inventor： Paraic Brannick ,  Colin G. Lyden ,  Damien J. McCartney ,  Gabriel Banarie

IPC: H02J7/00 ,  H03M1/20

CPC classification number: H02J7/007 ,  G04F10/005 ,  H02J7/345 ,  H03M1/201 ,  H03M1/50 ,  H03M1/52 ,  H03M1/60

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

公开(公告)号：US20160373128A1

公开(公告)日：2016-12-22

申请号：US15121381

申请日：2015-01-28

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE

Inventor： YAN WANG ,  GANG-YI HU ,  TAO LIU ,  YU-XIN WANG ,  JIAN-AN WANG ,  DONG-BING FU ,  TING LI ,  GUANG-BING CHEN

IPC: H03M1/20 ,  H03M1/10 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

Abstract: A dither circuit for high-resolution analog-to-digital converters(ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

Abstract translation: 提出了一种用于高分辨率模数转换器（ADC）的抖动电路，包括可设置的伪随机序列发生器，修整模块，可调节数模转换电路，抖动引入电路和抖动消除电路， 其中可设置伪随机序列发生器工作以产生与模拟输入信号不相关的伪随机序列信号，并且其输出可以被设置，其中n位输出被用作数字抖动信号，并且n可以小于ADC的量化比特; 修整模块用于确定可调节数模转换电路的微调信号，以将数字抖动信号精确地转换为模拟抖动信号; 引入抖动的电路用于将模拟抖动信号引入ADC; 抖动消除电路用于从ADC的输出中去除数字抖动信号。 抖动电路具有较低的复杂度和更高的动态性能，适用于高分辨率ADC。

公开(公告)号：US09455667B2

公开(公告)日：2016-09-27

申请号：US14831781

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03M1/82 ,  H03B5/12 ,  H03B1/00 ,  H03K3/015 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03L7/093 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。

公开(公告)号：US09374036B2

公开(公告)日：2016-06-21

申请号：US14831091

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B5/12 ,  H03B1/00 ,  H03K3/015 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03L7/093 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US20160056827A1

公开(公告)日：2016-02-25

申请号：US14831784

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03L7/093 ,  G04F10/00 ,  H03M1/20 ,  H03M1/00

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。

公开(公告)号：US09077366B2

公开(公告)日：2015-07-07

申请号：US13969549

申请日：2013-08-17

Applicant: Broadcom Corporation

Inventor： Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

IPC: H03M1/12 ,  H03M1/20 ,  H03M3/00

CPC classification number: H03M1/201 ,  H03M3/332 ,  H03M3/396 ,  H03M3/406 ,  H03M3/456

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract translation: 技术和设备在两个或多个信号频率或频率手中提供模数转换，并且可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。 可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号 接收机应用。

公开(公告)号：US08963750B2

公开(公告)日：2015-02-24

申请号：US14258102

申请日：2014-04-22

Applicant: Asahi Kasei Microdevices Corporation

Inventor： David Canard ,  Julien Delorme

IPC: H03M1/20 ,  H03L7/093

CPC classification number: H03M1/201 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/18

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract translation: 描述了使用基于时间数字转换器TDC（20）的基于延迟元件的布置的时间 - 数字转换方案，其中抖动内置在数字域中并被引入模拟域中作为电源的调制 电压（TDC电源）提供TDC的延迟元件，每个延迟元件具有表现出对其电源电压的依赖性的传播延迟。

公开(公告)号：US20140132430A1

公开(公告)日：2014-05-15

申请号：US14162559

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper STEENSGAARD-MADSEN

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。

公开(公告)号：US20140022103A1

公开(公告)日：2014-01-23

申请号：US13940819

申请日：2013-07-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keisuke KIMURA ,  Tatsuji MATSUURA ,  Yuichi OKUDA ,  Hideo NAKANE ,  Takaya YAMAMOTO

IPC: H03M1/20

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US20120326904A1

公开(公告)日：2012-12-27

申请号：US13170155

申请日：2011-06-27

Applicant: Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

Inventor： Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

IPC: H03M1/20 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M3/332 ,  H03M3/396 ,  H03M3/406 ,  H03M3/456

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract translation: 技术和设备在两个或多个信号频率或频带上提供模数转换，并可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。 可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号 接收机应用。