公开(公告)号：US20190341924A1

公开(公告)日：2019-11-07

申请号：US16475117

申请日：2016-06-01

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： TING LI ,  GANG-YI HU ,  RU-ZHANG LI ,  JIAN-AN WANG ,  YONG ZHANG ,  ZHENG-BO HUANG ,  GUANG-BING CHEN ,  YU-XIN WANG ,  DONG-BING FU ,  YAN WANG ,  JUN YUAN

IPC: H03M1/06

Abstract: A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

公开(公告)号：US20160373128A1

公开(公告)日：2016-12-22

申请号：US15121381

申请日：2015-01-28

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE

Inventor： YAN WANG ,  GANG-YI HU ,  TAO LIU ,  YU-XIN WANG ,  JIAN-AN WANG ,  DONG-BING FU ,  TING LI ,  GUANG-BING CHEN

IPC: H03M1/20 ,  H03M1/10 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

Abstract: A dither circuit for high-resolution analog-to-digital converters(ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

Abstract translation: 提出了一种用于高分辨率模数转换器（ADC）的抖动电路，包括可设置的伪随机序列发生器，修整模块，可调节数模转换电路，抖动引入电路和抖动消除电路， 其中可设置伪随机序列发生器工作以产生与模拟输入信号不相关的伪随机序列信号，并且其输出可以被设置，其中n位输出被用作数字抖动信号，并且n可以小于ADC的量化比特; 修整模块用于确定可调节数模转换电路的微调信号，以将数字抖动信号精确地转换为模拟抖动信号; 引入抖动的电路用于将模拟抖动信号引入ADC; 抖动消除电路用于从ADC的输出中去除数字抖动信号。 抖动电路具有较低的复杂度和更高的动态性能，适用于高分辨率ADC。

公开(公告)号：US20180076824A1

公开(公告)日：2018-03-15

申请号：US15559055

申请日：2015-06-08

Applicant: China Electronic Technology Corporation, 24th Research Institute

Inventor： TING LI ,  GANGYI HU ,  HEQUAN JIANG ,  RUZHANG LI ,  ZHENGBO HUANG ,  YONG ZHANG ,  GUANGBING CHEN ,  YUXIN WANG ,  DONGBING FU

IPC: H03M1/46 ,  H03M1/80 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/42

CPC classification number: H03M1/468 ,  H03M1/0678 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/42 ,  H03M1/804

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

公开(公告)号：US20150370952A1

公开(公告)日：2015-12-24

申请号：US14396737

申请日：2013-11-28

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： YAN WANG ,  YU-XIN WANG ,  GANG-YI HU ,  TING LI ,  TAO LIU ,  GUANG-BING CHEN

IPC: G06F17/50 ,  H01G4/38

CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  H01G4/38 ,  H01G15/00 ,  H03M1/164 ,  H03M1/442

Abstract: A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.

Abstract translation: 提供一种用于产生电容器阵列的布局设计方法，其分为四个步骤：首先，确定单元电容器的布线模式，允许将导线连接到上板与下板平行;第二，电容器阵列布局为 设计有电容分布在Mh线，Mh是电容器线的最大值，单相电容器阵列中定义了1类至K类电容器的线数;第三，为电容器阵列设置了布线模式，确保长度 到单元电容器的上板和下板的电线相等，最后，寄生参数以验证布局的方式进行表征。 还提供电容器阵列。 通过消除由寄生电容引起的电容失配，该方法可以以简单有效的方式产生良好匹配的电容器阵列。

公开(公告)号：US20160112059A1

公开(公告)日：2016-04-21

申请号：US14890160

申请日：2014-05-05

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： TING LI ,  RU-ZHANG LI ,  YONG ZHANG ,  ZHENG-BO HUANG ,  GUANG-BING CHEN ,  JIAN-AN WANG ,  YU-XIN WANG ,  DONG-BING FU ,  YAN WANG ,  XU WANG

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/42

CPC classification number: H03M1/0675 ,  H03M1/0678 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/42 ,  H03M1/468 ,  H03M1/687

Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

Abstract translation: 提供了逐次逼近的模数转换器及其转换方法，逐次逼近模数转换器包括具有冗余位的分段多级电容器阵列，比较器，加权存储电路，代码重构 电路和控制逻辑电路。 逐次逼近模数转换器有助于降低电路设计的复杂性，具有体积小，功耗低的特点。 没有辅助电容阵列，开关和控制逻辑，该电路可以用来精确测量和纠正电容器失配误差。