公开(公告)号：US20190341924A1

公开(公告)日：2019-11-07

申请号：US16475117

申请日：2016-06-01

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： TING LI ,  GANG-YI HU ,  RU-ZHANG LI ,  JIAN-AN WANG ,  YONG ZHANG ,  ZHENG-BO HUANG ,  GUANG-BING CHEN ,  YU-XIN WANG ,  DONG-BING FU ,  YAN WANG ,  JUN YUAN

IPC: H03M1/06

Abstract: A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

公开(公告)号：US20190334514A1

公开(公告)日：2019-10-31

申请号：US16475123

申请日：2016-07-07

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： DAI-GUO XU ,  GANG-YI HU ,  RU-ZHANG LI ,  JIAN-AN WANG ,  GUANG-BING CHEN ,  YU-XIN WANG ,  DONG-BING FU ,  TAO LIU

IPC: H03K5/24 ,  H03K19/003 ,  H03K19/00

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

公开(公告)号：US20160373128A1

公开(公告)日：2016-12-22

申请号：US15121381

申请日：2015-01-28

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE

Inventor： YAN WANG ,  GANG-YI HU ,  TAO LIU ,  YU-XIN WANG ,  JIAN-AN WANG ,  DONG-BING FU ,  TING LI ,  GUANG-BING CHEN

IPC: H03M1/20 ,  H03M1/10 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

Abstract: A dither circuit for high-resolution analog-to-digital converters(ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

Abstract translation: 提出了一种用于高分辨率模数转换器（ADC）的抖动电路，包括可设置的伪随机序列发生器，修整模块，可调节数模转换电路，抖动引入电路和抖动消除电路， 其中可设置伪随机序列发生器工作以产生与模拟输入信号不相关的伪随机序列信号，并且其输出可以被设置，其中n位输出被用作数字抖动信号，并且n可以小于ADC的量化比特; 修整模块用于确定可调节数模转换电路的微调信号，以将数字抖动信号精确地转换为模拟抖动信号; 引入抖动的电路用于将模拟抖动信号引入ADC; 抖动消除电路用于从ADC的输出中去除数字抖动信号。 抖动电路具有较低的复杂度和更高的动态性能，适用于高分辨率ADC。

公开(公告)号：US20190334538A1

公开(公告)日：2019-10-31

申请号：US16475120

申请日：2016-06-17

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： JIE PU ,  GANG-YI HU ,  DONG-BING FU ,  XI CHEN ,  XING-FA HUANG ,  YU-XIN WANG ,  GUANG-BING CHEN ,  RU-ZHANG LI

IPC: H03M1/10 ,  H03M1/06

Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

公开(公告)号：US20190356325A1

公开(公告)日：2019-11-21

申请号：US16476106

申请日：2016-06-27

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： RONG-BIN HU ,  YONG-LU WANG ,  GANG-YI HU ,  HE-QUAN JIANG ,  ZHENG-PING ZHANG ,  GUANG-BING CHEN ,  DONG-BING FU ,  YU-XIN WANG ,  LEI ZHANG ,  RONG-KE YE ,  CAN ZHU ,  YU-HAN GAO

IPC: H03M1/06 ,  H03K5/24

Abstract: A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

公开(公告)号：US20190190257A1

公开(公告)日：2019-06-20

申请号：US16310451

申请日：2016-06-22

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： YAN WANG ,  TAO LIU ,  GUANG-BING CHEN ,  YU-XIN WANG ,  DONG-BING FU ,  YU-JUN YANG ,  LIANG CHEN ,  YANG PU

IPC: H02H9/04 ,  H01L27/02 ,  H01L23/00

CPC classification number: H02H9/046 ,  H01L24/09 ,  H01L27/0248 ,  H02H9/00 ,  H05F3/02

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

公开(公告)号：US20160112059A1

公开(公告)日：2016-04-21

申请号：US14890160

申请日：2014-05-05

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： TING LI ,  RU-ZHANG LI ,  YONG ZHANG ,  ZHENG-BO HUANG ,  GUANG-BING CHEN ,  JIAN-AN WANG ,  YU-XIN WANG ,  DONG-BING FU ,  YAN WANG ,  XU WANG

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/42

CPC classification number: H03M1/0675 ,  H03M1/0678 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/42 ,  H03M1/468 ,  H03M1/687

Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

Abstract translation: 提供了逐次逼近的模数转换器及其转换方法，逐次逼近模数转换器包括具有冗余位的分段多级电容器阵列，比较器，加权存储电路，代码重构 电路和控制逻辑电路。 逐次逼近模数转换器有助于降低电路设计的复杂性，具有体积小，功耗低的特点。 没有辅助电容阵列，开关和控制逻辑，该电路可以用来精确测量和纠正电容器失配误差。