公开(公告)号：US20190334514A1

公开(公告)日：2019-10-31

申请号：US16475123

申请日：2016-07-07

Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Inventor： DAI-GUO XU ,  GANG-YI HU ,  RU-ZHANG LI ,  JIAN-AN WANG ,  GUANG-BING CHEN ,  YU-XIN WANG ,  DONG-BING FU ,  TAO LIU

IPC: H03K5/24 ,  H03K19/003 ,  H03K19/00

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.