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    DITHER CIRCUIT FOR HIGH-RESOLUTION ANALOG-TO-DIGITAL CONVERTERS
    1.
    发明申请
    DITHER CIRCUIT FOR HIGH-RESOLUTION ANALOG-TO-DIGITAL CONVERTERS 有权
    用于高分辨率模拟数字转换器的电路

    公开(公告)号：US20160373128A1

    公开(公告)日：2016-12-22

    申请号：US15121381

    申请日：2015-01-28

    Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE

    Inventor： YAN WANG ,  GANG-YI HU ,  TAO LIU ,  YU-XIN WANG ,  JIAN-AN WANG ,  DONG-BING FU ,  TING LI ,  GUANG-BING CHEN

    IPC: H03M1/20 ,  H03M1/10 ,  H03M1/46 ,  H03M1/12

    CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

    Abstract: A dither circuit for high-resolution analog-to-digital converters(ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

    Abstract translation: 提出了一种用于高分辨率模数转换器（ADC）的抖动电路，包括可设置的伪随机序列发生器，修整模块，可调节数模转换电路，抖动引入电路和抖动消除电路， 其中可设置伪随机序列发生器工作以产生与模拟输入信号不相关的伪随机序列信号，并且其输出可以被设置，其中n位输出被用作数字抖动信号，并且n可以小于ADC的量化比特; 修整模块用于确定可调节数模转换电路的微调信号，以将数字抖动信号精确地转换为模拟抖动信号; 引入抖动的电路用于将模拟抖动信号引入ADC; 抖动消除电路用于从ADC的输出中去除数字抖动信号。 抖动电路具有较低的复杂度和更高的动态性能，适用于高分辨率ADC。

    CAPACITOR ARRAY AND LAYOUT DESIGN METHOD THEREOF
    4.
    发明申请
    CAPACITOR ARRAY AND LAYOUT DESIGN METHOD THEREOF 有权
    电容阵列和布局设计方法

    公开(公告)号：US20150370952A1

    公开(公告)日：2015-12-24

    申请号：US14396737

    申请日：2013-11-28

    Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

    Inventor： YAN WANG ,  YU-XIN WANG ,  GANG-YI HU ,  TING LI ,  TAO LIU ,  GUANG-BING CHEN

    IPC: G06F17/50 ,  H01G4/38

    CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  H01G4/38 ,  H01G15/00 ,  H03M1/164 ,  H03M1/442

    Abstract: A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.

    Abstract translation: 提供一种用于产生电容器阵列的布局设计方法，其分为四个步骤：首先，确定单元电容器的布线模式，允许将导线连接到上板与下板平行;第二，电容器阵列布局为 设计有电容分布在Mh线，Mh是电容器线的最大值，单相电容器阵列中定义了1类至K类电容器的线数;第三，为电容器阵列设置了布线模式，确保长度 到单元电容器的上板和下板的电线相等，最后，寄生参数以验证布局的方式进行表征。 还提供电容器阵列。 通过消除由寄生电容引起的电容失配，该方法可以以简单有效的方式产生良好匹配的电容器阵列。

    TRANSCONDUCTANCE AMPLIFIER BASED ON SELF-BIASED CASCODE STRUCTURE
    5.
    发明申请
    TRANSCONDUCTANCE AMPLIFIER BASED ON SELF-BIASED CASCODE STRUCTURE 有权

    公开(公告)号：US20210305943A1

    公开(公告)日：2021-09-30

    申请号：US16625671

    申请日：2016-01-26

    Applicant: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

    Inventor： DAIGUO XU ,  GANGYI HU ,  RUZHANG LI ,  JIAN'AN WANG ,  GUANGBING CHEN ,  YUXIN WANG ,  TAO LIU ,  LU LIU ,  MINMING DENG ,  HANFU SHI ,  XU WANG

    IPC: H03F1/22

    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor MO that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor Cc, a higher figure of merit is achieved.

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