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    Digital Oversampling Clock And Data Recovery Circuit
    2.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20190379524A1

    公开(公告)日：2019-12-12

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    System and method of improving blocking immunity of radio frequency transceiver front end
    4.
    发明授权
    System and method of improving blocking immunity of radio frequency transceiver front end 有权

    公开(公告)号：US11196385B2

    公开(公告)日：2021-12-07

    申请号：US16793985

    申请日：2020-02-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Ruifeng Sun ,  Ricky Setiawan ,  Ben Wee-Guan Tan

    IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193

    Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

    Digital oversampling clock and data recovery circuit
    5.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10826677B2

    公开(公告)日：2020-11-03

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    6.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20180152280A1

    公开(公告)日：2018-05-31

    申请号：US15884650

    申请日：2018-01-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    7.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 有权

    公开(公告)号：US20170366330A1

    公开(公告)日：2017-12-21

    申请号：US15182951

    申请日：2016-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    POWER-SAVING POWER ARCHITECTURE FOR INTEGRATED CIRCUITS SUCH AS MICROCONTROLLERS
    9.
    发明申请
    POWER-SAVING POWER ARCHITECTURE FOR INTEGRATED CIRCUITS SUCH AS MICROCONTROLLERS 有权

    公开(公告)号：US20210311540A1

    公开(公告)日：2021-10-07

    申请号：US16841138

    申请日：2020-04-06

    Applicant: Silicon Laboratories Inc.

    Inventor： Rex Tak Ying Wong ,  Ricky Setiawan ,  Hua Beng Chan ,  Yushan Jiang ,  Pio Balmelli

    IPC: G06F1/3237 ,  H02M1/00 ,  G06F1/3234 ,  G06F1/28 ,  G06F1/3296

    Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.

    SYSTEM AND METHOD OF IMPROVING BLOCKING IMMUNITY OF RADIO FREQUENCY TRANSCEIVER FRONT END
    10.
    发明申请
    SYSTEM AND METHOD OF IMPROVING BLOCKING IMMUNITY OF RADIO FREQUENCY TRANSCEIVER FRONT END 有权

    公开(公告)号：US20210257970A1

    公开(公告)日：2021-08-19

    申请号：US16793985

    申请日：2020-02-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Ruifeng Sun ,  Ricky Setiawan ,  Ben Wee-Guan Tan

    IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21

    Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

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