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公开(公告)号：US11144104B2
公开(公告)日：2021-10-12
申请号：US16791210
申请日：2020-02-14
Applicant: Silicon Laboratories Inc.
Inventor： Rex Tak Ying Wong , Michael R. May , Pio Balmelli
IPC: G06F1/26 , G06F13/40 , G01R19/165 , G06F11/22
Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.
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2.发明申请公开(公告)号：US20190339729A1
公开(公告)日：2019-11-07
申请号：US15968996
申请日：2018-05-02
Applicant: Silicon Laboratories Inc.
Inventor： Adrianus Bink , Wajid Hassan Minhass , Pio Balmelli , Ricky Setiawan
IPC: G05F3/08
Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.
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公开(公告)号：US20210311540A1
公开(公告)日：2021-10-07
申请号：US16841138
申请日：2020-04-06
Applicant: Silicon Laboratories Inc.
Inventor： Rex Tak Ying Wong , Ricky Setiawan , Hua Beng Chan , Yushan Jiang , Pio Balmelli
IPC: G06F1/3237 , H02M1/00 , G06F1/3234 , G06F1/28 , G06F1/3296
Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.
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公开(公告)号：US20210282088A1
公开(公告)日：2021-09-09
申请号：US17329496
申请日：2021-05-25
Applicant: Silicon Laboratories Inc.
Inventor： Pio Balmelli , Praveen Vangala , John M. Khoury
IPC: H04W52/02
Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.
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公开(公告)号：US20210255678A1
公开(公告)日：2021-08-19
申请号：US16791210
申请日：2020-02-14
Applicant: Silicon Laboratories Inc.
Inventor： Rex Tak Ying Wong , Michael R. May , Pio Balmelli
IPC: G06F1/26 , G01R19/165 , G06F13/40
Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.
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Patent Agency Ranking
公开(公告)号：US20140361838A1
公开(公告)日：2014-12-11
申请号：US13910392
申请日：2013-06-05
Applicant: Silicon Laboratories Inc.
Inventor： Yu Su , Mustafa H. Koroglu , Ruifeng Sun , Krishna Pentakota , Pio Balmelli , Ramin Khoini-Poorfard
Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.
Abstract translation: 放大器包括负增益放大器，负载元件和跨导器件。 负增益放大器具有输入和输出。 负载元件具有耦合到电源电压端子的第一端子和第二端子。 跨导器件具有耦合到负载元件的第二端子的第一电流电极，耦合到负增益放大器的输出的控制电极和耦合到负增益放大器的输入的第二电流电极。
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公开(公告)号：US12192903B2
公开(公告)日：2025-01-07
申请号：US17329496
申请日：2021-05-25
Applicant: Silicon Laboratories Inc.
Inventor： Pio Balmelli , Praveen Vangala , John M. Khoury
IPC: H04W52/02
Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.
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公开(公告)号：US11057834B2
公开(公告)日：2021-07-06
申请号：US16226423
申请日：2018-12-19
Applicant: Silicon Laboratories Inc.
Inventor： Pio Balmelli , Praveen Vangala , John M. Khoury
IPC: H04W52/02
Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.
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9.发明授权公开(公告)号：US10579087B2
公开(公告)日：2020-03-03
申请号：US15968996
申请日：2018-05-02
Applicant: Silicon Laboratories Inc.
Inventor： Adrianus Bink , Wajid Hassan Minhass , Pio Balmelli , Ricky Setiawan
IPC: G05F3/08
Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.
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公开(公告)号：US09231579B2
公开(公告)日：2016-01-05
申请号：US14074241
申请日：2013-11-07
Applicant: SILICON LABORATORIES INC.
Inventor： Ruifeng Sun , Mustafa H. Koroglu , Ramin Khoini Poorfard , Yu Su , Krishna Pentakota , Pio Balmelli
CPC classification number: H03K17/16 , H03K2217/0063
Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.
Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。
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