-
公开(公告)号：US09231579B2
公开(公告)日：2016-01-05
申请号：US14074241
申请日：2013-11-07
Applicant: SILICON LABORATORIES INC.
Inventor： Ruifeng Sun , Mustafa H. Koroglu , Ramin Khoini Poorfard , Yu Su , Krishna Pentakota , Pio Balmelli
CPC classification number: H03K17/16 , H03K2217/0063
Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.
Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。
-
公开(公告)号：US20230006621A1
公开(公告)日：2023-01-05
申请号：US17363049
申请日：2021-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Sherry Wu , Michael S. Johnson , Vitor Pereira
Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
-
3.发明授权公开(公告)号：US11196385B2
公开(公告)日：2021-12-07
申请号：US16793985
申请日：2020-02-18
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Ricky Setiawan , Ben Wee-Guan Tan
Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.
-
公开(公告)号：US10658999B1
公开(公告)日：2020-05-19
申请号：US16506409
申请日：2019-07-09
Applicant: Silicon Laboratories Inc.
Inventor： Essam S. Atalla , Ruifeng Sun , Mohamed M. Elkholy
Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.
-
公开(公告)号：US10033421B2
公开(公告)日：2018-07-24
申请号：US15168318
申请日：2016-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Vitor Pereira , Mustafa Koroglu , Ruifeng Sun , Ramin Khoini-Poorfard , Abdulkerim Coban , Yu Su , Krishna Pentakota
Abstract: In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.
-
Patent Agency Ranking
公开(公告)号：US20140361838A1
公开(公告)日：2014-12-11
申请号：US13910392
申请日：2013-06-05
Applicant: Silicon Laboratories Inc.
Inventor： Yu Su , Mustafa H. Koroglu , Ruifeng Sun , Krishna Pentakota , Pio Balmelli , Ramin Khoini-Poorfard
Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.
Abstract translation: 放大器包括负增益放大器，负载元件和跨导器件。 负增益放大器具有输入和输出。 负载元件具有耦合到电源电压端子的第一端子和第二端子。 跨导器件具有耦合到负载元件的第二端子的第一电流电极，耦合到负增益放大器的输出的控制电极和耦合到负增益放大器的输入的第二电流电极。
-
公开(公告)号：US11025231B1
公开(公告)日：2021-06-01
申请号：US16850215
申请日：2020-04-16
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Abdulkerim Coban
Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.
-
公开(公告)号：US20150123714A1
公开(公告)日：2015-05-07
申请号：US14074241
申请日：2013-11-07
Applicant: SILICON LABORATORIES INC.
Inventor： Ruifeng Sun , Mustafa H. Koroglu , Ramin Khoini Poorfard , Yu Su , Krishna Pentakota , Pio Balmelli
IPC: H03K17/16
CPC classification number: H03K17/16 , H03K2217/0063
Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.
Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。
-
公开(公告)号：US20230208368A1
公开(公告)日：2023-06-29
申请号：US18175593
申请日：2023-02-28
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Sherry Wu , Michael S. Johnson , Vitor Pereira
CPC classification number: H03F3/245 , H03F1/0233 , H04B1/04 , H04L27/12 , H04B2001/0408 , H03F2200/105 , H03F2200/451
Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
-
公开(公告)号：US11646705B2
公开(公告)日：2023-05-09
申请号：US17363049
申请日：2021-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Sherry Wu , Michael S. Johnson , Vitor Pereira
CPC classification number: H03F3/245 , H03F1/0233 , H04B1/04 , H04L27/12 , H03F2200/105 , H03F2200/451 , H04B2001/0408
Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.022 seconds)
