公开(公告)号：US20190181875A1

公开(公告)日：2019-06-13

申请号：US15777608

申请日：2016-11-10

Applicant: SOCIETE FRANCAISE DE DETECTEURS INFRARAOUGES - SOFRADIR

Inventor： Gilbert DECAENS

IPC: H03M1/16

CPC classification number: H03M1/162 ,  H03M1/168

Abstract: The analog-to-digital converter includes a first stage in which a voltage to be converted is applied to the input of a first comparator. The first comparator delivers, on a first digital output, a first digital result representative of the comparison between the voltage to be converted and the comparison voltage. The first digital output is connected to a calculator of a first intermediate voltage. A second comparator compares the first intermediate voltage with the comparison voltage and delivers a second digital result on a second digital output terminal. The second digital output terminal is connected to a second calculator of residual voltage that is a function of the voltage to be converted, of first and second voltages and of the first and second digital results. The first calculator is formed by the second calculator.

公开(公告)号：US20170155398A1

公开(公告)日：2017-06-01

申请号：US14954577

申请日：2015-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram NARAYANAN ,  Srinath RAMASWAMY ,  Arup POLLEY ,  Ajit SHARMA

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0609 ,  H03M1/001 ,  H03M1/002 ,  H03M1/1295 ,  H03M1/162

Abstract: An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.

公开(公告)号：US09337856B1

公开(公告)日：2016-05-10

申请号：US14867201

申请日：2015-09-28

Applicant: Nishant Dhawan ,  Kenton Veeder

Inventor： Nishant Dhawan ,  Kenton Veeder

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/56

CPC classification number: H03M1/56 ,  H03M1/0697 ,  H03M1/1038 ,  H03M1/162 ,  H03M1/52 ,  H03M2201/2355

Abstract: Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope SN such that S1=K1·SN, S2=K2·SN, . . . SN-1=KN-1·SN-1 where the K values are integers, and the code count for conversion is C=K1·C1+K2·C2+ . . . KN-1·CN-1+CN where each Ci represents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C11, charging and discharging on the remaining slopes up to K2 to KN-1 for a number of counts per slope, Ci1 e.g. C21 to CN-1,1, discharging the remaining voltage residue on the shallowest slope and note the count, CN,1, sampling the same voltage on the ADC for a second calibration pass, discharging the voltage on the steepest slope for a modified number of counter counts C12=C11+/−X, modifying the number of charge/discharge counts time Ci2 for the slopes K2 to KN-1 to adjust for the change expected from the modified steep slope discharge to reach the shallowest slope with the same expected residue as for the first calibration pass, discharging the remaining voltage residue on the shallowest slope and note the actual count, CN,2, adjusting K1 to K1a based on the difference between CN,1 and CN,2, and; using C=K1a·C1+K2·C2+ . . . KN-1·CN-1+CN as the count code for conversion.

Abstract translation: 用于校准单斜坡多斜率模数转换器（SRMS ADC）的方法和系统，ADC包括不同时间常数即斜率的计数器和多个N个充电和放电元件，其中斜率之间的关系被定义为函数 的最小斜率SN，使得S1 = K1·SN，S2 = K2·SN。 。 。 SN-1 = KN-1·SN-1，其中K值是整数，转换代码计数为C = K1·C1 + K2·C2 +。 。 。 KN-1·CN-1 + CN，其中每个Ci表示转化每个斜率的观测计数，包括： 用于第一次校准的采样通过ADC传递电压，将最大斜率上的电压放电多个计数器计数C11，在其余斜率上的充电和放电达到K2至KN-1，对每个斜率计数Ci1 例如 C21至CN-1,1，放电最浅斜率上的剩余电压，并注意计数CN，1，对ADC进行相同的电压采样，进行第二次校准通过，将最陡坡上的电压放电至修改后的数字 计数器计数C12 = C11 +/- X，修改斜率K2至KN-1的充电/放电计数时间Ci2的数量，以调整从修改的陡倾斜放电预期的变化，以达到具有相同预期残留的最浅斜率 对于第一次校准通过，将最小斜坡上的剩余电压残余放电，并根据CN，1和CN，2之间的差值，注意实际计数CN，2调整K1至K1a; 使用C = K1a·C1 + K2·C2 +。 。 。 KN-1·CN-1 + CN作为转换计数码。

公开(公告)号：US09252800B1

公开(公告)日：2016-02-02

申请号：US14462916

申请日：2014-08-19

Applicant: Texas Instruments Incorporated

Inventor： Joonsung Park ,  Krishnaswamy Nagaraj ,  Mikel Ash

IPC: H03M1/38 ,  H03M1/20 ,  H03M1/46

CPC classification number: H03M1/20 ,  H03M1/162 ,  H03M1/38 ,  H03M1/462

Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

Abstract translation: 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。

公开(公告)号：US09054732B2

公开(公告)日：2015-06-09

申请号：US14249973

申请日：2014-04-10

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Tomoya Kakamu

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/44

CPC classification number: H03M1/38 ,  H03M1/129 ,  H03M1/162 ,  H03M1/206 ,  H03M1/44 ,  H03M1/468

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at ¼ or ¾ of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract translation: SAR模数转换电路包括：第一和第二CDAC; 分别比较第一和第二CDAC的输出，第一和第三CDAC的输出电平与参考电平的第一至第三比较器; 算术运算电路; SAR控制电路，其中所述SAR控制电路：在每个步骤中确定在四个范围中的哪一个范围中包括所述第一和第二CDAC的采样和保持的信号的输出电平，与所述转换范围相对应的四个范围被分配， 确定数字数据的两位，并调整第一和第二CDAC的输出电平，使得电压范围的1/4或¾的电平与中间电平一致，并且控制第一和第二开关，使得电压范围被设置为 作为下一步的转换范围。

公开(公告)号：US20140014821A1

公开(公告)日：2014-01-16

申请号：US13985723

申请日：2012-02-17

Applicant: Shoji Kawahito

Inventor： Shoji Kawahito

IPC: H03M1/18 ,  H04N5/378

CPC classification number: H03M1/18 ,  H03M1/162 ,  H03M1/403 ,  H03M1/56 ,  H03M3/39 ,  H03M3/46 ,  H04N5/378

Abstract: According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration.

Abstract translation: 根据该A / D转换器，通过在相同的电路配置中的操作程序的控制来实现用于执行积分A / D转换和用于执行循环A / D转换的第二A / D转换操作的第一A / D转换操作 。 此外，在第一A / D转换操作中，由于在输出信号的积分中使用的电容器的容量大于用于存储输入模拟信号和标准参考电压的电容器的容量，所以模拟信号 在积分A / D转换中输入根据容量比衰减并进行采样和积分。 因此，根据电容器的容量比，在积分A / D转换中输出的模拟信号的电压范围也降低，因此可以以单端配置构建A / D转换器。

公开(公告)号：US08547461B2

公开(公告)日：2013-10-01

申请号：US13240670

申请日：2011-09-22

Applicant: Wun-Ki Jung ,  Seung-Hyun Lim ,  Dong-Hun Lee ,  Kwi-Sung Yoo ,  Min-Ho Kwon ,  Chi-Ho Hwang

Inventor： Wun-Ki Jung ,  Seung-Hyun Lim ,  Dong-Hun Lee ,  Kwi-Sung Yoo ,  Min-Ho Kwon ,  Chi-Ho Hwang

IPC: H04N3/14 ,  H03M1/12

CPC classification number: H04N5/378 ,  H03M1/162 ,  H03M1/56 ,  H04N5/3575 ,  H04N5/374

Abstract: An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.

Abstract translation: 模数转换器包括比较信号生成单元和控制单元。 比较信号生成单元通过在第一比较模式中基于开关控制信号比较输入信号与所选择的参考信号，并且通过基于开关控制将差分电压与斜坡信号进行比较来确定比较信号的逻辑电平 信号在第二比较模式。 基于输入信号和所选择的参考信号产生差分电压，使得差分电压的电平低于与第二比较模式中所选参考信号的电压电平相对应的精细电压电平。 控制单元基于比较信号和模式选择信号产生开关控制信号。

公开(公告)号：US08487801B2

公开(公告)日：2013-07-16

申请号：US13435178

申请日：2012-03-30

Applicant: Shinichirou Etou ,  Yasuhide Shimizu ,  Kouhei Kudou ,  Yukitoshi Yamashita

Inventor： Shinichirou Etou ,  Yasuhide Shimizu ,  Kouhei Kudou ,  Yukitoshi Yamashita

IPC: H03M1/12

CPC classification number: H03M1/1225 ,  H03M1/162

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N−m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract translation: 一种模数（A / D）转换器包括：粗A / D转换器，被配置为当将模拟输入信号转换为N位数字信号时，将模拟输入信号转换成高阶m位 数字信号; 配置为基于粗略A / D转换器的转换结果将模拟输入信号转换成低阶n位（其中n = N-m）数字信号的精细A / D转换器; 以及轨道保持（TH）电路，被配置为对所述模拟输入信号进行采样，以将与粗略A / D转换器的粗略参考电压相比较的比较电压提供给与比较电压相比较的精细参考电压 基于精细A / D转换器对精细A / D转换器的转换结果。 TH电路被配置为在模拟输入信号，粗参考电压和精细参考电压的选择输入路径中共享采样电容器。

公开(公告)号：US20130120180A1

公开(公告)日：2013-05-16

申请号：US13697162

申请日：2011-05-13

Applicant: Shoji Kawahito

Inventor： Shoji Kawahito

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/145 ,  H03M1/162 ,  H03M1/403 ,  H03M1/56 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/378

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract translation: A / D转换器101包括第一循环A / D转换器电路103和A / D转换器电路105.A / D转换器101包括用于存储来自A / D转换器电路103,105的转换结果的记录电路107 记录电路107包括高位记录电路107a和下位电路107b。 循环A / D转换电路103接收模拟值SA，并生成表示模拟值SA的第一数字值SD1和残差值RD。 A / D转换电路105接收剩余值RD，并产生具有低M位的第二数字值SD2，表示剩余值RD。 A / D转换电路105的转换精度可以降低到A / D转换电路103中的1/2L。

公开(公告)号：US20130069808A1

公开(公告)日：2013-03-21

申请号：US13618443

申请日：2012-09-14

Applicant: Chandrashekar A. Reddy ,  Yagneshwara Ramakrishna Rao Vadapalli

Inventor： Chandrashekar A. Reddy ,  Yagneshwara Ramakrishna Rao Vadapalli

IPC: H03M1/06 ,  H03M1/14 ,  H03M1/66

CPC classification number: H03M1/1019 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/442

Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N−3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.

Abstract translation: 一种用于信号处理的系统，包括具有第一级和第二级的循环模/数转换器结构，其中第一级被配置为接收输入信号以执行1.5位/级ADC并产生第一级输出信号，以及 第二级被配置为接收第一级输出信号并且使用最终转换阶段执行精细偏移调谐。 第二级还被配置为执行1.5位/级ADC并产生反馈到第一级的第二级输出，以迭代地生成下一个1.5位，直到N位数据的（N-3）个最高有效位为 生成。 第三级，被配置为使用闪存ADC采样电路产生N位数据的三个最低有效位，所述闪速ADC采样电路在第一级的输出端采样残留信号。