公开(公告)号：US20240249950A1

公开(公告)日：2024-07-25

申请号：US18449452

申请日：2023-08-14

Applicant: Western Digital Technologies, Inc.

Inventor： Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L21/3065 ,  H01L21/82 ,  H01L23/00

CPC classification number: H01L21/3065 ,  H01L21/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2924/20641

Abstract: Approaches directed at increasing the production yield of integrated circuits including layers of low-k dielectrics. One example provides a flip-chip assembly including a semiconductor chip attached to a substrate using pillars or bumps. The semiconductor chip has a thickness profile such that the chip is thinner near the corners than in middle portions. The thinner corner portions beneficially alleviate chip-integrity issues related to the stresses generated during the solder reflow operation while the thicker middle portions beneficially alleviate chip-integrity issues related to the stresses generated during the chip or die pick-up operation. Due to the alleviation of both types of chip-integrity issues, the number of instances in which the low-k dielectrics crack during the corresponding assembly operations is significantly reduced, thereby beneficially increasing the manufacturing yield.

公开(公告)号：US20240243113A1

公开(公告)日：2024-07-18

申请号：US18096174

申请日：2023-01-12

Applicant: Apple Inc.

Inventor： Sidharth S. Dalmia

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/16225

Abstract: A system-in-package for an electronic device with a reduced thickness is presented herein. The system-in-package includes a stepped mold, an insulation film substrate, at least one processor die, and at least one passive element. The insulation film substrate is connected to a multi-layer board via a first plurality of connectors. The at least one processor die is integrated into the stepped mold and stacked onto the insulation film substrate via a second plurality of connectors. The at least one passive element is integrated into the stepped mold and stacked onto the insulation film substrate.

公开(公告)号：US20240243110A1

公开(公告)日：2024-07-18

申请号：US18235643

申请日：2023-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  SUNGEUN JO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2225/1005 ,  H01L2924/1438 ,  H01L2924/16235

Abstract: Disclosed is a semiconductor package comprising an interposer substrate, a chip stack on the interposer substrate and including first semiconductor chips that are vertically stacked, a second semiconductor chip on the interposer substrate and horizontally spaced apart from the chip stack, a molding layer on the interposer substrate and surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and a plurality of conductive posts that vertically penetrate the molding layer and connect the interposer substrate to the redistribution layer.

公开(公告)号：US20240241231A1

公开(公告)日：2024-07-18

申请号：US18391655

申请日：2023-12-21

Applicant: Meta Platforms Technologies, LLC

Inventor： Jack Diepen Mumbo ,  Rajendra D. Pendse ,  Alexandra Gualdino ,  Jaspreet Singh Gandhi ,  Jeremiah Nyaribo ,  Harish Venkataraman ,  Gregory Cohoon

IPC: G01S7/4865 ,  G01S7/481 ,  G01S17/10 ,  H01L23/00 ,  H01L31/107

CPC classification number: G01S7/4865 ,  G01S7/4811 ,  G01S17/10 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L31/107 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/73207 ,  H01L2924/12041

Abstract: A time-of-flight (ToF) module includes a light source, a driver module, and a light sensor. The driver module includes electrical circuitry configured to selectively drive the light source to emit pulsed illumination light. The light sensor is configured to sense returning light reflected from a target. At least one of the light source, driver module, and light sensor is stacked on another to reduce a footprint of the ToF module.

公开(公告)号：US20240234362A9

公开(公告)日：2024-07-11

申请号：US18477910

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolan KWON ,  Jingyu MOON

IPC: H01L23/00 ,  B23K3/02

CPC classification number: H01L24/75 ,  B23K3/025 ,  B23K2101/40 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75621

Abstract: Semiconductor manufacturing equipment including a main body having a bonding head, a head heater at a bottom of the bonding head, the head heater including a thermal compression surface, negative pressure channels recessed from the thermal compression surface and the negative pressure channels including holes therein, and a bonding tool having a first surface, a second surface, grooves at the first surface, the first surface configured to contact the thermal compression surface, and the second surface opposite to the first surface contacting a semiconductor chip for thermal compression may be provided.

公开(公告)号：US20240234270A1

公开(公告)日：2024-07-11

申请号：US18395626

申请日：2023-12-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh KIM ,  JinHee JUNG ,  OMin KWON

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/165 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor device and a method for making the same are provided. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein a plurality of conductive pillars are formed on the second surface of the substrate; forming a polyimide layer on the second surface of the substrate to cover the plurality of conductive pillars; mounting a first electronic component on the first surface of the substrate; and forming a first encapsulant on the first surface of the substrate to cover the first electronic component.

公开(公告)号：US20240222310A1

公开(公告)日：2024-07-04

申请号：US18090922

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory OSTROWICKI ,  Amit NANGIA ,  Kashyap MOHAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L21/565 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2924/351

Abstract: In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuitry region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.

公开(公告)号：US20240222222A1

公开(公告)日：2024-07-04

申请号：US18399127

申请日：2023-12-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Gaius Gillman Fountain, JR.

IPC: H01L23/433 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L24/08 ,  H01L25/0652 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/16151 ,  H01L2924/16196 ,  H01L2924/16235 ,  H01L2924/16251

Abstract: A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

公开(公告)号：US20240213100A1

公开(公告)日：2024-06-27

申请号：US18087879

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Chiao-ti Huang ,  Bishwajit Debnath ,  Anupama Bowonder ,  Matthew J. Prince

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823878 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L24/16 ,  H01L2224/16225

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. The gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. The inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.

公开(公告)号：US12021189B2

公开(公告)日：2024-06-25

申请号：US18203242

申请日：2023-05-30

Applicant: CORNING INCORPORATED

Inventor： Michael Edward Badding ,  Jacqueline Leslie Brown ,  Jennifer Anella Heine ,  Thomas Dale Ketcham ,  Gary Edward Merz ,  Eric Lee Miller ,  Zhen Song ,  Cameron Wayne Tanner ,  Conor James Walsh

IPC: H01M10/052 ,  B28B1/30 ,  C04B35/622 ,  G02B6/122 ,  H01M4/04 ,  H01M4/131 ,  H01M4/136 ,  H01M4/1391 ,  H01M4/505 ,  H01M10/0525 ,  H01M10/0562 ,  H01M4/02 ,  H01M4/1397 ,  H01M4/525 ,  H01M4/58

CPC classification number: H01M10/0562 ,  B28B1/30 ,  C04B35/62218 ,  G02B6/122 ,  H01M4/0471 ,  H01M4/131 ,  H01M4/1391 ,  H01M4/505 ,  H01M10/0525 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/181 ,  H01M2004/028 ,  H01M4/136 ,  H01M4/1397 ,  H01M4/525 ,  H01M4/5825 ,  H01M10/052 ,  H01M2300/0071 ,  H01M2300/0077 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A cathode configured for a solid-state battery includes a body having grains of inorganic material sintered to one another, wherein the grains comprise lithium. A thickness of the body is from 3 μm to 100 μm. The first major surface and the second major surface have an unpolished granular profile such that the profile includes grains protruding outward from the respective major surface with a height of at least 25 nm and no more than 150 μm relative to recessed portions of the respective major surface at boundaries between the respective grains.