公开(公告)号：US20240213100A1

公开(公告)日：2024-06-27

申请号：US18087879

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Chiao-ti Huang ,  Bishwajit Debnath ,  Anupama Bowonder ,  Matthew J. Prince

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823878 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L24/16 ,  H01L2224/16225

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. The gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. The inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.