公开(公告)号：US20150214384A1

公开(公告)日：2015-07-30

申请号：US14681753

申请日：2015-04-08

Applicant: The Trustees of Columbia University in the City of New York

Inventor： KENNETH L. SHEPARD ,  Jacob Rosenstein ,  Ryan Michael Field ,  Dan Fleischer

IPC: H01L29/808 ,  H01L21/762 ,  H01L29/423 ,  H01L27/098 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/808 ,  H01L21/762 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/42316 ,  H01L29/66893

Abstract: A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a substrate layer of one dopant type with a gate layer of that dopant type disposed on the substrate, a depletion channel of a second dopant type disposed on the first gate layer, and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor. The second gate layer can separate the depletion channel from the surface, and the depletion channel separates the first gate layer from the second gate layer.

Abstract translation: 互补金属氧化物半导体（CMOS） - 集成结型场效应晶体管（JFET）具有减小的尺寸和降低的噪声。 示例性JFET具有一种掺杂剂型的衬底层，其中设置在衬底上的该掺杂剂类型的栅极层，设置在第一栅极层上的第二掺杂剂类型的耗尽沟道和设置在第一掺杂剂类型的第二栅极层 在耗尽通道上并且靠近晶体管的表面。 第二栅极层可以将耗尽沟道与表面分开，耗尽沟道将第一栅极层与第二栅极层分开。

公开(公告)号：US09076885B2

公开(公告)日：2015-07-07

申请号：US14560294

申请日：2014-12-04

Applicant: ROHM CO., LTD.

Inventor： Kenichi Yoshimochi

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7806 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66666 ,  H01L29/7813

Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.

Abstract translation: 提供了可以以低成本制造并且可以减少反向泄漏电流的半导体器件及其制造方法。 半导体器件具有：源极区域和漏极区域，其间具有主体区域; 源沟槽，其到达身体区域，穿透源区域; 形成在所述源沟槽的底部的体接触区域; 源极电极嵌入在源沟槽中; 以及面向身体区域的栅电极。 半导体器件还具有：用于二极管的n型区域; 形成到二极管的n型区域的二极管沟槽; 用于二极管的p +区，其与二极管沟槽底部的二极管的n型区域形成pn结; 以及与二极管沟槽的侧壁处的二极管的n型区域形成肖特基结的肖特基电极。

公开(公告)号：US09023705B1

公开(公告)日：2015-05-05

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/423 ,  H01L27/088 ,  H01L27/105 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US09006046B2

公开(公告)日：2015-04-14

申请号：US13975453

申请日：2013-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Makoto Furuno

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/06 ,  H01L29/49 ,  H01L27/115 ,  H01L27/12 ,  C23C14/00 ,  H01L21/02 ,  C23C14/08 ,  H01L49/02 ,  C23C14/34 ,  H01L29/786

CPC classification number: H01L21/02266 ,  C23C14/0036 ,  C23C14/08 ,  C23C14/3407 ,  C23C14/3414 ,  H01L21/02112 ,  H01L21/8232 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1251 ,  H01L28/60 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78645 ,  H01L29/7869

Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.

Abstract translation: 本发明的目的是提供一种通过DC溅射法形成氧化镓膜的沉积方法。 另一个目的是提供一种使用氧化镓膜作为绝缘层的半导体器件的制造方法，例如晶体管的栅极绝缘层。 使用包含氧化镓（也称为GaOX）的氧化物靶，通过DC溅射法或脉冲DC溅射法形成绝缘膜。 氧化物靶包括GaOX，X小于1.5，优选大于或等于0.01且小于或等于0.5，进一步优选大于或等于0.1且小于或等于0.2。 氧化物靶具有导电性，并且在氧气气氛或氧气和稀有气体如氩气的混合气氛中进行溅射。

公开(公告)号：US20150021669A1

公开(公告)日：2015-01-22

申请号：US14505102

申请日：2014-10-02

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

Inventor： Mieno FUMITAKE

IPC: H01L29/808 ,  H01L29/43 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L27/098 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1066 ,  H01L29/43 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/66901 ,  H01L29/808

Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

Abstract translation: 提供了具有薄翅片结构的非平面JFET器件。 翅片从基底的顶表面向上突出或通过其顶表面形成，其中鳍具有由第一导电类型的第一半导体材料形成的第一半导体层部分。 第一半导体层部分具有源极区和漏极区，在源极区和漏极区之间延伸的沟道区。 形成邻近沟道区的两个或更多个沟道控制区，用于在沟道区中产生电荷耗尽区，并延伸到沟道区，从而控制通过沟道区的电流。 提供了一个栅极，以便从沟道控制区域的外侧邻接和短路至少两个通道控制区域。

公开(公告)号：US08917547B2

公开(公告)日：2014-12-23

申请号：US13954206

申请日：2013-07-30

Applicant: International Business Machines Corporation

Inventor： Jin Cai ,  Leland Chang ,  Jeffrey W. Sleight

IPC: G11C11/34 ,  H01L21/8232 ,  G11C11/40 ,  H01L27/12

CPC classification number: G11C11/40 ,  G11C11/411 ,  H01L21/8232 ,  H01L27/1203

Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

Abstract translation: 包括在SOI衬底上制造的SOI衬底和横向双极结型晶体管（BJT）的存储器阵列。 BJT形成第一和第二反相器交叉耦合以形成存储单元。 读出电路输出存储单元的二进制状态。 电源被配置为向读取电路提供Vdd电压，并将Vcc和Vee电压提供给第一组横向双极晶体管和第二组横向双极晶体管，其中Vee电压至少为零伏， Vcc电压大于Vee电压并且等于或小于Vdd电压。

公开(公告)号：US20140342684A1

公开(公告)日：2014-11-20

申请号：US14449448

申请日：2014-08-01

Applicant: Ioannis Papananos

Inventor： Ioannis Papananos

IPC: H04B1/10 ,  H04B1/16

CPC classification number: H04B1/10 ,  H01L21/8232 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165 ,  H03D7/18 ,  H03D2200/0082 ,  H04B1/16

Abstract: A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is manufactured in a variety of silicon processes. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM, operative at radio frequencies (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF− signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO− signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO− signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.

Abstract translation: 能够以非常高的频率工作的图像拒绝混合器（IRM）的被动实现在各种硅工艺中制造。 IRM包括四极MOS乘法器和集总元件混合电路，产生无源IRM，在几GHz的射频（RF）下工作，中频（IF）为几GHz。 RF +和RF信号被提供给两个四个MOS乘法器。 使用本地振荡器信号（LO）来向乘法器之一提供LO +和LO信号，并且通过向移相器提供LO，产生的是提供给另一乘法器的90度移位的LO +和LO信号。 为混合器提供两个乘法器的输出并从每个混合电路中选择适当的IF信号，确保被动IRM的正常运行。

公开(公告)号：US08871583B2

公开(公告)日：2014-10-28

申请号：US13675759

申请日：2012-11-13

Applicant: Semiconductor Manufacturing International Corporation ,  Semiconductor Manufacturing International Corporation

Inventor： Mieno Fumitake

IPC: H01L21/336 ,  H01L27/098 ,  H01L29/808 ,  H01L27/12 ,  H01L29/06 ,  H01L21/8232 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L27/098 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1066 ,  H01L29/43 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/66901 ,  H01L29/808

Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

Abstract translation: 提供了具有薄翅片结构的非平面JFET器件。 翅片从基底的顶表面向上突出或通过其顶表面形成，其中鳍具有由第一导电类型的第一半导体材料形成的第一半导体层部分。 第一半导体层部分具有源极区和漏极区，在源极区和漏极区之间延伸的沟道区。 形成邻近沟道区的两个或更多个沟道控制区，用于在沟道区中产生电荷耗尽区，并延伸到沟道区，从而控制通过沟道区的电流。 提供了一个栅极，以便从沟道控制区域的外侧邻接和短路至少两个通道控制区域。

公开(公告)号：US20140153328A1

公开(公告)日：2014-06-05

申请号：US13691823

申请日：2012-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Cai ,  Leland Chang ,  Jeffrey W. Sleight

IPC: G11C11/40

CPC classification number: G11C11/40 ,  G11C11/411 ,  H01L21/8232 ,  H01L27/1203

Abstract: An example embodiment is a memory array. The memory array includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

Abstract translation: 示例性实施例是存储器阵列。 存储器阵列包括在SOI衬底上制造的SOI衬底和横向双极结型晶体管（BJT）。 BJT形成第一和第二反相器交叉耦合以形成存储单元。 读出电路输出存储单元的二进制状态。 电源被配置为向读取电路提供Vdd电压，并将Vcc和Vee电压提供给第一组横向双极晶体管和第二组横向双极晶体管，其中Vee电压至少为零伏， Vcc电压大于Vee电压并且等于或小于Vdd电压。

公开(公告)号：US08502280B2

公开(公告)日：2013-08-06

申请号：US13086246

申请日：2011-04-13

Applicant: Badih El-Kareh ,  Leonard Forbes

Inventor： Badih El-Kareh ,  Leonard Forbes

IPC: H01L29/66

CPC classification number: H01L27/0617 ,  H01L21/8232 ,  H01L21/845 ,  H01L27/085 ,  H01L27/0922 ,  H01L27/098 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7832 ,  H01L29/785 ,  H01L29/8086

Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.