公开(公告)号：US11798626B2

公开(公告)日：2023-10-24

申请号：US17947320

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon Kim ,  Junyoung Ko ,  Sangwan Nam ,  Minjae Seo ,  Jiwon Seo ,  Hojun Lee

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/20 ,  G11C16/16 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

公开(公告)号：US11791003B2

公开(公告)日：2023-10-17

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US11783897B2

公开(公告)日：2023-10-10

申请号：US17875001

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

公开(公告)号：US20230307071A1

公开(公告)日：2023-09-28

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US11769555B2

公开(公告)日：2023-09-26

申请号：US17443726

申请日：2021-07-27

Applicant: SK hynix Inc.

Inventor： Haobo Wang ,  Aman Bhatia ,  Fan Zhang

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/08 ,  G11C16/26 ,  G06F7/544

CPC classification number: G11C16/3404 ,  G06N3/08 ,  G11C16/102 ,  G11C16/26 ,  G06F7/5443

Abstract: Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with reduced number of processing. A controller receives first and second program voltage (PV) levels associated with read operations on cells. The controller estimates first and second probability distribution parameter sets representing skew normal distributions of the first and second PV levels, respectively. The controller estimates an optimal read threshold voltage based on the first and second probability distribution parameter sets. The optimal read threshold voltage is a read threshold voltage such that first probability density function (PDF) value of the skew normal distribution of the first PV level is the same as the second PDF value of the skew normal distribution of the second PV level.

公开(公告)号：US20230298678A1

公开(公告)日：2023-09-21

申请号：US17699508

申请日：2022-03-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Dengtao Zhao

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/28 ,  G11C16/08

Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.

公开(公告)号：US20230260583A1

公开(公告)日：2023-08-17

申请号：US17670821

申请日：2022-02-14

Applicant: SanDisk Technologies LLC

Inventor： Xiaojia JIA ,  Swaroop KAZA ,  Laidong WANG ,  Jiacen GUO

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/24

Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.

公开(公告)号：US11728005B2

公开(公告)日：2023-08-15

申请号：US17903371

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Yen Chun Lee ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C16/3404 ,  G11C29/12005 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

公开(公告)号：US11715534B2

公开(公告)日：2023-08-01

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Reiko Sumi ,  Reika Tanaka ,  Masumi Saitoh

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US11705211B2

公开(公告)日：2023-07-18

申请号：US17415646

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/22 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.